]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-hw.git/history - jx1.sch
CAN termination & merging redesigned, added connectors, power regulators, user I/O
[fpga/zynq/canbench-hw.git] / jx1.sch
2016-04-05 Martin JerabekCAN termination & merging redesigned, added connectors...
2016-03-15 Martin JerabekUsed MicroHeaders from kicad-parts