2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
5 --------------------------------------------------------------------------------
9 W : integer := 16); -- Event port width (pin count)
11 -- Peripheral bus interface
12 ACK_O : out std_logic;
14 DAT_I : in std_logic_vector (W-1 downto 0);
15 DAT_O : out std_logic_vector (W-1 downto 0);
21 EVENT_I : in std_logic_vector (W-1 downto 0);
22 EVENT_O : out std_logic_vector (W-1 downto 0));
25 --------------------------------------------------------------------------------
27 architecture behavioral of event_rwc is
29 signal status : std_logic_vector (W-1 downto 0) := (others => '0');
30 signal write_en : std_logic;
34 ACK_O <= SEL_I and STB_I;
39 write_en <= SEL_I and STB_I and WE_I;
41 process (CLK_I, RST_I) is
43 if rising_edge(CLK_I) then
45 status <= (others => '0');
47 if write_en = '1' then
48 status <= (status and not DAT_I) or EVENT_I;
50 status <= status or EVENT_I;