msp430_cmdproc.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.all;
   4 use ieee.std_logic_unsigned.all;
   5
   6 --------------------------------------------------------------------------------
   7
   8 entity msp430_cmdproc is
   9   port (
  10     -- Clock & reset
  11     CLK_24MHz : in  std_logic;
  12     RESET     : in  std_logic;
  13     -- RS232
  14     RXD       : in  std_logic;
  15     TXD       : out std_logic);
  16 end msp430_cmdproc;
  17
  18 --------------------------------------------------------------------------------
  19
  20 architecture rtl of msp430_cmdproc is
  21
  22 --------------------------------------------------------------------------------
  23
  24 begin
  25   -- Soft-core MCU
  26   openMSP430_1 : entity work.openMSP430_8_32_mul
  27     port map (
  28       dco_clk                  => CLK_24MHz,
  29       lfxt_clk                 => '0',
  30       reset_n                  => RESET,
  31       rxd                      => RXD,
  32       txd                      => TXD,
  33       per_addr                 => open,
  34       per_din                  => open,
  35       per_dout                 => (others => '0'),
  36       per_wen                  => open,
  37       per_en                   => open,
  38       nmi                      => '0',
  39       irq                      => (others => '0'),
  40       irq_acc                  => open,
  41       aclk_en                  => open,
  42       smclk_en                 => open,
  43       mclk                     => open,
  44       puc                      => open);
  45
  46 end rtl;
  47