library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

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entity msp430_cmdproc is
  port (
    -- Clock & reset
    CLK_24MHz : in  std_logic;
    RESET     : in  std_logic;
    -- RS232
    RXD       : in  std_logic;
    TXD       : out std_logic);
end msp430_cmdproc;

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architecture rtl of msp430_cmdproc is

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begin
  -- Soft-core MCU
  openMSP430_1 : entity work.openMSP430_8_32_mul
    port map (
      dco_clk                  => CLK_24MHz,
      lfxt_clk                 => '0',
      reset_n                  => RESET,
      rxd                      => RXD,
      txd                      => TXD,
      per_addr                 => open,
      per_din                  => open,
      per_dout                 => (others => '0'),
      per_wen                  => open,
      per_en                   => open,
      nmi                      => '0',
      irq                      => (others => '0'),
      irq_acc                  => open,
      aclk_en                  => open,
      smclk_en                 => open,
      mclk                     => open,
      puc                      => open);

end rtl;