--- /dev/null
+# Date: Sat Jan 8 21:37:24 2011
+SET addpads = False
+SET asysymbol = True
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc2v1000
+SET devicefamily = virtex2
+SET flowvendor = Foundation_iSE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -6
+SET verilogsim = False
+SET vhdlsim = True
+SET workingdirectory = /home/vladimir/xilinx/leds_v/coregen/tmp/
+
--- /dev/null
+Version 4
+SymbolType BLOCK
+RECTANGLE Normal 32 0 320 272
+PIN 0 48 LEFT 36
+PINATTR PinName addr[8:0]
+PINATTR Polarity IN
+LINE Wide 0 48 32 48
+PIN 0 80 LEFT 36
+PINATTR PinName din[7:0]
+PINATTR Polarity IN
+LINE Wide 0 80 32 80
+PIN 0 112 LEFT 36
+PINATTR PinName we
+PINATTR Polarity IN
+LINE Normal 0 112 32 112
+PIN 0 144 LEFT 36
+PINATTR PinName en
+PINATTR Polarity IN
+LINE Normal 0 144 32 144
+PIN 0 240 LEFT 36
+PINATTR PinName clk
+PINATTR Polarity IN
+LINE Normal 0 240 32 240
+PIN 352 48 RIGHT 36
+PINATTR PinName dout[7:0]
+PINATTR Polarity OUT
+LINE Wide 320 48 352 48
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
+$g1x52=#Zl|b
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--- /dev/null
+VERSION 5
+BEGIN SYMBOL ram_8x512
+SYMBOLTYPE BLOCK
+TIMESTAMP 2011 1 8 22 4 20
+SYMPIN 0 48 Input addr[8:0]
+SYMPIN 0 80 Input din[7:0]
+SYMPIN 0 112 Input we
+SYMPIN 0 144 Input en
+SYMPIN 0 240 Input clk
+SYMPIN 352 48 Output dout[7:0]
+RECTANGLE N 32 0 320 272
+BEGIN DISPLAY 36 48 PIN addr[8:0] ATTR PinName
+ FONT 24 "Arial"
+END DISPLAY
+BEGIN LINE W 0 48 32 48
+END LINE
+BEGIN DISPLAY 36 80 PIN din[7:0] ATTR PinName
+ FONT 24 "Arial"
+END DISPLAY
+BEGIN LINE W 0 80 32 80
+END LINE
+BEGIN DISPLAY 36 112 PIN we ATTR PinName
+ FONT 24 "Arial"
+END DISPLAY
+LINE N 0 112 32 112
+BEGIN DISPLAY 36 144 PIN en ATTR PinName
+ FONT 24 "Arial"
+END DISPLAY
+LINE N 0 144 32 144
+BEGIN DISPLAY 36 240 PIN clk ATTR PinName
+ FONT 24 "Arial"
+END DISPLAY
+LINE N 0 240 32 240
+BEGIN DISPLAY 316 48 PIN dout[7:0] ATTR PinName
+ ALIGNMENT RIGHT
+ FONT 24 "Arial"
+END DISPLAY
+BEGIN LINE W 320 48 352 48
+END LINE
+END SYMBOL
--- /dev/null
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used --
+-- solely for design, simulation, implementation and creation of --
+-- design files limited to Xilinx devices or technologies. Use --
+-- with non-Xilinx devices or technologies is expressly prohibited --
+-- and immediately terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
+-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
+-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
+-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
+-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
+-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
+-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
+-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
+-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
+-- FOR A PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support --
+-- appliances, devices, or systems. Use in such applications are --
+-- expressly prohibited. --
+-- --
+-- (c) Copyright 1995-2007 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file ram_8x512.vhd when simulating
+-- the core, ram_8x512. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY ram_8x512 IS
+ port (
+ addr: IN std_logic_VECTOR(8 downto 0);
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(7 downto 0);
+ dout: OUT std_logic_VECTOR(7 downto 0);
+ en: IN std_logic;
+ we: IN std_logic);
+END ram_8x512;
+
+ARCHITECTURE ram_8x512_a OF ram_8x512 IS
+-- synthesis translate_off
+component wrapped_ram_8x512
+ port (
+ addr: IN std_logic_VECTOR(8 downto 0);
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(7 downto 0);
+ dout: OUT std_logic_VECTOR(7 downto 0);
+ en: IN std_logic;
+ we: IN std_logic);
+end component;
+
+-- Configuration specification
+ for all : wrapped_ram_8x512 use entity XilinxCoreLib.blkmemsp_v6_2(behavioral)
+ generic map(
+ c_sinit_value => "0",
+ c_has_en => 1,
+ c_reg_inputs => 0,
+ c_yclk_is_rising => 1,
+ c_ysinit_is_high => 1,
+ c_ywe_is_high => 0,
+ c_yprimitive_type => "16kx1",
+ c_ytop_addr => "1024",
+ c_yhierarchy => "hierarchy1",
+ c_has_limit_data_pitch => 0,
+ c_has_rdy => 0,
+ c_write_mode => 0,
+ c_width => 8,
+ c_yuse_single_primitive => 0,
+ c_has_nd => 0,
+ c_has_we => 1,
+ c_enable_rlocs => 0,
+ c_has_rfd => 0,
+ c_has_din => 1,
+ c_ybottom_addr => "0",
+ c_pipe_stages => 0,
+ c_yen_is_high => 0,
+ c_depth => 512,
+ c_has_default_data => 1,
+ c_limit_data_pitch => 18,
+ c_has_sinit => 0,
+ c_yydisable_warnings => 1,
+ c_mem_init_file => "mif_file_16_1",
+ c_default_data => "0",
+ c_ymake_bmm => 0,
+ c_addr_width => 9);
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_ram_8x512
+ port map (
+ addr => addr,
+ clk => clk,
+ din => din,
+ dout => dout,
+ en => en,
+ we => we);
+-- synthesis translate_on
+
+END ram_8x512_a;
+
--- /dev/null
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used --
+-- solely for design, simulation, implementation and creation of --
+-- design files limited to Xilinx devices or technologies. Use --
+-- with non-Xilinx devices or technologies is expressly prohibited --
+-- and immediately terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
+-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
+-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
+-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
+-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
+-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
+-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
+-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
+-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
+-- FOR A PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support --
+-- appliances, devices, or systems. Use in such applications are --
+-- expressly prohibited. --
+-- --
+-- (c) Copyright 1995-2007 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+-- The following code must appear in the VHDL architecture header:
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component ram_8x512
+ port (
+ addr: IN std_logic_VECTOR(8 downto 0);
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(7 downto 0);
+ dout: OUT std_logic_VECTOR(7 downto 0);
+ en: IN std_logic;
+ we: IN std_logic);
+end component;
+
+-- Synplicity black box declaration
+attribute syn_black_box : boolean;
+attribute syn_black_box of ram_8x512: component is true;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : ram_8x512
+ port map (
+ addr => addr,
+ clk => clk,
+ din => din,
+ dout => dout,
+ en => en,
+ we => we);
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
+
+-- You must compile the wrapper file ram_8x512.vhd when simulating
+-- the core, ram_8x512. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
--- /dev/null
+##############################################################
+#
+# Xilinx Core Generator version J.36
+# Date: Sat Jan 8 22:04:28 2011
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = True
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc2v1000
+SET devicefamily = virtex2
+SET flowvendor = Foundation_iSE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -6
+SET verilogsim = False
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2
+# END Select
+# BEGIN Parameters
+CSET active_clock_edge=Rising_Edge_Triggered
+CSET additional_output_pipe_stages=0
+CSET component_name=ram_8x512
+CSET depth=512
+CSET disable_warning_messages=true
+CSET enable_pin=true
+CSET enable_pin_polarity=Active_Low
+CSET global_init_value=0
+CSET handshaking_pins=false
+CSET has_limit_data_pitch=false
+CSET init_pin=false
+CSET init_value=0
+CSET initialization_pin_polarity=Active_High
+CSET limit_data_pitch=18
+CSET load_init_file=false
+CSET port_configuration=Read_And_Write
+CSET primitive_selection=Optimize_For_Area
+CSET register_inputs=false
+CSET select_primitive=16kx1
+CSET width=8
+CSET write_enable_polarity=Active_Low
+CSET write_mode=Read_After_Write
+# END Parameters
+GENERATE
+# CRC: 85636b95
+
--- /dev/null
+# Output products list for <ram_8x512>
+ram_8x512.vho
+ram_8x512.asy
+ram_8x512.sym
+ram_8x512_xmdf.tcl
+ram_8x512_flist.txt
+ram_8x512.vhd
+ram_8x512.ngc
+ram_8x512.xco
--- /dev/null
+The following files were generated for 'ram_8x512' in directory
+coregen/:
+
+ram_8x512.vho:
+ VHO template file containing code that can be used as a model for
+ instantiating a CORE Generator module in a VHDL design.
+
+ram_8x512.asy:
+ Graphical symbol information file. Used by the ISE tools and some
+ third party tools to create a symbol representing the core.
+
+ram_8x512.sym:
+ Please see the core data sheet.
+
+ram_8x512_xmdf.tcl:
+ Please see the core data sheet.
+
+ram_8x512_flist.txt:
+ Text file listing all of the output files produced when a customized
+ core was generated in the CORE Generator.
+
+ram_8x512.vhd:
+ VHDL wrapper file provided to support functional simulation. This
+ file contains simulation model customization data that is passed to
+ a parameterized simulation model for the core.
+
+ram_8x512.ngc:
+ Binary Xilinx implementation netlist file containing the information
+ required to implement the module in a Xilinx (R) FPGA.
+
+ram_8x512_readme.txt:
+ Text file indicating the files generated and how they are used.
+
+ram_8x512.xco:
+ CORE Generator input file containing the parameters used to
+ regenerate a core.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
--- /dev/null
+# The package naming convention is <core_name>_xmdf
+package provide ram_8x512_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::ram_8x512_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::ram_8x512_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name ram_8x512
+}
+# ::ram_8x512_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::ram_8x512_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512.vho
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512.sym
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module ram_8x512
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
--- /dev/null
+Version 4
+SymbolType BLOCK
+RECTANGLE Normal 32 0 320 272
+PIN 0 48 LEFT 36
+PINATTR PinName addr[10:0]
+PINATTR Polarity IN
+LINE Wide 0 48 32 48
+PIN 0 80 LEFT 36
+PINATTR PinName din[7:0]
+PINATTR Polarity IN
+LINE Wide 0 80 32 80
+PIN 0 112 LEFT 36
+PINATTR PinName we
+PINATTR Polarity IN
+LINE Normal 0 112 32 112
+PIN 0 144 LEFT 36
+PINATTR PinName en
+PINATTR Polarity IN
+LINE Normal 0 144 32 144
+PIN 0 240 LEFT 36
+PINATTR PinName clk
+PINATTR Polarity IN
+LINE Normal 0 240 32 240
+PIN 352 48 RIGHT 36
+PINATTR PinName dout[7:0]
+PINATTR Polarity OUT
+LINE Wide 320 48 352 48
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
+$g;x52=#Zl|b
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\ No newline at end of file
--- /dev/null
+VERSION 5
+BEGIN SYMBOL rom_8x2k
+SYMBOLTYPE BLOCK
+TIMESTAMP 2011 1 8 22 4 37
+SYMPIN 0 48 Input addr[10:0]
+SYMPIN 0 80 Input din[7:0]
+SYMPIN 0 112 Input we
+SYMPIN 0 144 Input en
+SYMPIN 0 240 Input clk
+SYMPIN 352 48 Output dout[7:0]
+RECTANGLE N 32 0 320 272
+BEGIN DISPLAY 36 48 PIN addr[10:0] ATTR PinName
+ FONT 24 "Arial"
+END DISPLAY
+BEGIN LINE W 0 48 32 48
+END LINE
+BEGIN DISPLAY 36 80 PIN din[7:0] ATTR PinName
+ FONT 24 "Arial"
+END DISPLAY
+BEGIN LINE W 0 80 32 80
+END LINE
+BEGIN DISPLAY 36 112 PIN we ATTR PinName
+ FONT 24 "Arial"
+END DISPLAY
+LINE N 0 112 32 112
+BEGIN DISPLAY 36 144 PIN en ATTR PinName
+ FONT 24 "Arial"
+END DISPLAY
+LINE N 0 144 32 144
+BEGIN DISPLAY 36 240 PIN clk ATTR PinName
+ FONT 24 "Arial"
+END DISPLAY
+LINE N 0 240 32 240
+BEGIN DISPLAY 316 48 PIN dout[7:0] ATTR PinName
+ ALIGNMENT RIGHT
+ FONT 24 "Arial"
+END DISPLAY
+BEGIN LINE W 320 48 352 48
+END LINE
+END SYMBOL
--- /dev/null
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used --
+-- solely for design, simulation, implementation and creation of --
+-- design files limited to Xilinx devices or technologies. Use --
+-- with non-Xilinx devices or technologies is expressly prohibited --
+-- and immediately terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
+-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
+-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
+-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
+-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
+-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
+-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
+-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
+-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
+-- FOR A PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support --
+-- appliances, devices, or systems. Use in such applications are --
+-- expressly prohibited. --
+-- --
+-- (c) Copyright 1995-2007 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file rom_8x2k.vhd when simulating
+-- the core, rom_8x2k. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY rom_8x2k IS
+ port (
+ addr: IN std_logic_VECTOR(10 downto 0);
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(7 downto 0);
+ dout: OUT std_logic_VECTOR(7 downto 0);
+ en: IN std_logic;
+ we: IN std_logic);
+END rom_8x2k;
+
+ARCHITECTURE rom_8x2k_a OF rom_8x2k IS
+-- synthesis translate_off
+component wrapped_rom_8x2k
+ port (
+ addr: IN std_logic_VECTOR(10 downto 0);
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(7 downto 0);
+ dout: OUT std_logic_VECTOR(7 downto 0);
+ en: IN std_logic;
+ we: IN std_logic);
+end component;
+
+-- Configuration specification
+ for all : wrapped_rom_8x2k use entity XilinxCoreLib.blkmemsp_v6_2(behavioral)
+ generic map(
+ c_sinit_value => "0",
+ c_has_en => 1,
+ c_reg_inputs => 0,
+ c_yclk_is_rising => 1,
+ c_ysinit_is_high => 1,
+ c_ywe_is_high => 0,
+ c_yprimitive_type => "16kx1",
+ c_ytop_addr => "1024",
+ c_yhierarchy => "hierarchy1",
+ c_has_limit_data_pitch => 0,
+ c_has_rdy => 0,
+ c_write_mode => 0,
+ c_width => 8,
+ c_yuse_single_primitive => 0,
+ c_has_nd => 0,
+ c_has_we => 1,
+ c_enable_rlocs => 0,
+ c_has_rfd => 0,
+ c_has_din => 1,
+ c_ybottom_addr => "0",
+ c_pipe_stages => 0,
+ c_yen_is_high => 0,
+ c_depth => 2048,
+ c_has_default_data => 1,
+ c_limit_data_pitch => 18,
+ c_has_sinit => 0,
+ c_yydisable_warnings => 1,
+ c_mem_init_file => "mif_file_16_1",
+ c_default_data => "0",
+ c_ymake_bmm => 0,
+ c_addr_width => 11);
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_rom_8x2k
+ port map (
+ addr => addr,
+ clk => clk,
+ din => din,
+ dout => dout,
+ en => en,
+ we => we);
+-- synthesis translate_on
+
+END rom_8x2k_a;
+
--- /dev/null
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used --
+-- solely for design, simulation, implementation and creation of --
+-- design files limited to Xilinx devices or technologies. Use --
+-- with non-Xilinx devices or technologies is expressly prohibited --
+-- and immediately terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
+-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
+-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
+-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
+-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
+-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
+-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
+-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
+-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
+-- FOR A PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support --
+-- appliances, devices, or systems. Use in such applications are --
+-- expressly prohibited. --
+-- --
+-- (c) Copyright 1995-2007 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+-- The following code must appear in the VHDL architecture header:
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component rom_8x2k
+ port (
+ addr: IN std_logic_VECTOR(10 downto 0);
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(7 downto 0);
+ dout: OUT std_logic_VECTOR(7 downto 0);
+ en: IN std_logic;
+ we: IN std_logic);
+end component;
+
+-- Synplicity black box declaration
+attribute syn_black_box : boolean;
+attribute syn_black_box of rom_8x2k: component is true;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : rom_8x2k
+ port map (
+ addr => addr,
+ clk => clk,
+ din => din,
+ dout => dout,
+ en => en,
+ we => we);
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
+
+-- You must compile the wrapper file rom_8x2k.vhd when simulating
+-- the core, rom_8x2k. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
--- /dev/null
+##############################################################
+#
+# Xilinx Core Generator version J.36
+# Date: Sat Jan 8 22:04:43 2011
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = True
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc2v1000
+SET devicefamily = virtex2
+SET flowvendor = Foundation_iSE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -6
+SET verilogsim = False
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2
+# END Select
+# BEGIN Parameters
+CSET active_clock_edge=Rising_Edge_Triggered
+CSET additional_output_pipe_stages=0
+CSET component_name=rom_8x2k
+CSET depth=2048
+CSET disable_warning_messages=true
+CSET enable_pin=true
+CSET enable_pin_polarity=Active_Low
+CSET global_init_value=0
+CSET handshaking_pins=false
+CSET has_limit_data_pitch=false
+CSET init_pin=false
+CSET init_value=0
+CSET initialization_pin_polarity=Active_High
+CSET limit_data_pitch=18
+CSET load_init_file=false
+CSET port_configuration=Read_And_Write
+CSET primitive_selection=Optimize_For_Area
+CSET register_inputs=false
+CSET select_primitive=16kx1
+CSET width=8
+CSET write_enable_polarity=Active_Low
+CSET write_mode=Read_After_Write
+# END Parameters
+GENERATE
+# CRC: d4bb4e0b
+
--- /dev/null
+# Output products list for <rom_8x2k>
+rom_8x2k_xmdf.tcl
+rom_8x2k_flist.txt
+rom_8x2k.sym
+rom_8x2k.xco
+rom_8x2k.vho
+rom_8x2k.asy
+rom_8x2k.ngc
+rom_8x2k.vhd
--- /dev/null
+The following files were generated for 'rom_8x2k' in directory
+coregen/:
+
+rom_8x2k_xmdf.tcl:
+ Please see the core data sheet.
+
+rom_8x2k_flist.txt:
+ Text file listing all of the output files produced when a customized
+ core was generated in the CORE Generator.
+
+rom_8x2k.sym:
+ Please see the core data sheet.
+
+rom_8x2k.xco:
+ CORE Generator input file containing the parameters used to
+ regenerate a core.
+
+rom_8x2k.vho:
+ VHO template file containing code that can be used as a model for
+ instantiating a CORE Generator module in a VHDL design.
+
+rom_8x2k_readme.txt:
+ Text file indicating the files generated and how they are used.
+
+rom_8x2k.asy:
+ Graphical symbol information file. Used by the ISE tools and some
+ third party tools to create a symbol representing the core.
+
+rom_8x2k.ngc:
+ Binary Xilinx implementation netlist file containing the information
+ required to implement the module in a Xilinx (R) FPGA.
+
+rom_8x2k.vhd:
+ VHDL wrapper file provided to support functional simulation. This
+ file contains simulation model customization data that is passed to
+ a parameterized simulation model for the core.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
--- /dev/null
+# The package naming convention is <core_name>_xmdf
+package provide rom_8x2k_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::rom_8x2k_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::rom_8x2k_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name rom_8x2k
+}
+# ::rom_8x2k_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::rom_8x2k_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k.sym
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k.vho
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module rom_8x2k
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
projects / fpga / virtex2 / blink.git / commitdiff