+ Top level design

Design can be now implemented and downloaded to the target.

diff --git a/Makefile b/Makefile
new file mode 100644 (file)
index 0000000..2059ec3
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,142 @@
+# TOP           - Name of the top-level module
+# DEVICE        - Name of the FPGA device (device-package-speed)
+# PRJ           - Name of .prj file with names of all source files. See XST manual.
+# BMM           - If design contains initialized memories, softcore MCU, etc., this
+#                 file describes mapping of .elf file to these memories. Only one
+#                 .bmm file can be used.
+# ELF           - File containing initialization data of memories described by
+#                 previously defined .bmm file. Format can be .elf or .mem.
+# SEARCH_DIRS   - Directories to search when searching for netlists (.ngc, ...).
+#                 See NGDBUILD manual.
+# JTAG_POS      - Position of device in JTAG chain. Used when downloading bit stream.
+# INTSTYLE      - Style of screen output. (ise | xflow | silent)
+
+
+TOP             = openMSP430_fpga
+DEVICE          = xc2v1000-fg456
+
+PRJ                                                    = openMSP430_fpga.prj
+
+BMM             = memory.bmm
+ELF             = software/leds.elf
+
+SEARCH_DIRS     = coregen
+
+JTAG_POS        = 2
+INTSTYLE        = xflow
+
+
+ifneq (${strip ${BMM}},)
+       BITFILE = ${TOP}_rp.bit
+else
+  BITFILE = ${TOP}.bit
+endif
+
+#===============================================================================
+
+.PHONY: all synth ngdbuild map implement download clean
+
+all: clean implement
+
+implement: ${BITFILE}
+
+#===============================================================================
+
+synth ${TOP}.ngc: ${PRJ}
+       echo " \
+               run \
+               ${addprefix -ifn ,${PRJ}} \
+               -ifmt mixed \
+               -ofn ${TOP}.ngc \
+               -ofmt NGC \
+               -top ${TOP} \
+               -p ${DEVICE} \
+               -opt_mode Speed \
+               -opt_level 1" \
+       | xst
+
+
+ngdbuild ${TOP}.ngd: ${TOP}.ngc ${BMM} ${TOP}.ucf
+       ngdbuild \
+               ${addprefix -bm ,${BMM}} \
+               -intstyle ${INTSTYLE} \
+               -p ${DEVICE} \
+               -uc ${TOP}.ucf \
+               ${addprefix -sd ,${SEARCH_DIRS}} \
+               ${TOP}.ngc \
+               ${TOP}.ngd
+
+
+map ${TOP}.ncd: ${TOP}.ngd
+       map \
+               -p ${DEVICE} \
+               -intstyle ${INTSTYLE} \
+               ${TOP}.ngd \
+               ${TOP}.pcf
+       par \
+               -w ${TOP}.ncd \
+               -intstyle ${INTSTYLE} \
+               ${TOP}.ncd \
+               ${TOP}.pcf
+
+
+${TOP}.bit: ${TOP}.ncd
+       bitgen -w ${TOP}.ncd ${TOP}.bit ${TOP}.pcf
+
+${TOP}_rp.bit: ${TOP}.bit ${ELF}
+       data2mem -bm ${basename ${BMM}}_bd.bmm -bd ${ELF} -bt ${TOP}.bit -o b ${TOP}_rp.bit
+
+download: ${BITFILE}
+       /bin/echo -e "\
+       setMode -bscan \n\
+       cleancablelock \n\
+       setCable -port auto \n\
+       identify \n\
+       assignFile -p ${JTAG_POS} -file ${BITFILE} \n\
+       program -p ${JTAG_POS} \n\
+       exit" | impact -batch
+
+#===============================================================================
+
+clean:
+       rm -f _impactbatch.log
+       rm -f ${basename ${BMM}}_bd.bmm
+       rm -f netlist.lst
+       rm -f ${TOP}.bgn
+       rm -f ${TOP}.bit
+       rm -f ${TOP}.bld
+       rm -f ${TOP}.d
+       rm -f ${TOP}.drc
+       rm -f ${TOP}.lso
+       rm -f ${TOP}.map
+       rm -f ${TOP}.mrp
+       rm -f ${TOP}.ncd
+       rm -f ${TOP}.ngc
+       rm -f ${TOP}.ngd
+       rm -f ${TOP}.ngm
+       rm -f ${TOP}.pad
+       rm -f ${TOP}_pad.csv
+       rm -f ${TOP}_pad.txt
+       rm -f ${TOP}.par
+       rm -f ${TOP}.pcf
+       rm -f ${TOP}_rp.bit
+       rm -f ${TOP}_summary.xml
+       rm -f ${TOP}.unroutes
+       rm -f ${TOP}_usage.xml
+       rm -f ${TOP}.xpi
+       rm -rf xst
+
+#===============================================================================
+
+%.d: %.prj
+       sed -e 's/#.*//' \
+                       -e 's/[ \t][ \t]*/ /g' \
+                       -e 's/^ //' -e 's/ $$//' \
+                       -e 's|\(.*\) \(.*\) \(.*\)|$<: \3|' \
+                       <$< >$@
+
+%.prj:
+       touch $@
+
+include ${PRJ:.prj=.d}
+

diff --git a/openMSP430_fpga.prj b/openMSP430_fpga.prj
new file mode 100644 (file)
index 0000000..58de78a
--- /dev/null
+++ b/openMSP430_fpga.prj
@@ -0,0 +1,26 @@
+verilog work openmsp430/omsp_alu.v
+verilog work openmsp430/omsp_clock_module.v
+verilog work openmsp430/omsp_dbg.v
+verilog work openmsp430/omsp_dbg_hwbrk.v
+verilog work openmsp430/omsp_dbg_uart.v
+verilog work openmsp430/omsp_execution_unit.v
+verilog work openmsp430/omsp_frontend.v
+verilog work openmsp430/omsp_mem_backbone.v
+verilog work openmsp430/omsp_multiplier.v
+verilog work openmsp430/omsp_register_file.v
+verilog work openmsp430/omsp_sfr.v
+verilog work openmsp430/omsp_watchdog.v
+verilog work openmsp430/openMSP430.v
+verilog work openmsp430/openMSP430_undefines.v
+verilog work openmsp430/timescale.v
+
+verilog work openMSP430_defines.v
+
+verilog work openmsp430/periph/omsp_gpio.v
+verilog work openmsp430/periph/omsp_timerA.v
+
+vhdl work coregen/ram_8x512.vhd
+vhdl work coregen/rom_8x2k.vhd
+
+vhdl work openMSP430_fpga.vhd
+

diff --git a/openMSP430_fpga.ucf b/openMSP430_fpga.ucf
new file mode 100644 (file)
index 0000000..7649e6c
--- /dev/null
+++ b/openMSP430_fpga.ucf
@@ -0,0 +1,31 @@
+#==============================================================================#
+# Clock & Reset                                                                #
+#==============================================================================#
+
+# V munualu jsou piny prohozeny!
+#NET "CLK_100MHz"        LOC = "B11" |     PERIOD =  10.0 ns LOW   5.0 ns;
+NET "CLK_24MHz"         LOC = "A11" |     PERIOD =  41.7 ns LOW  20.9 ns;
+
+NET "RESET"             LOC = "B6";
+
+
+#==============================================================================#
+# 7-Segment Display                                                            #
+#==============================================================================#
+
+NET "DISPLAY1<0>"       LOC = "D9";
+NET "DISPLAY1<1>"       LOC = "C9";
+NET "DISPLAY1<2>"       LOC = "F11";
+NET "DISPLAY1<3>"       LOC = "F9";
+NET "DISPLAY1<4>"       LOC = "F10";
+NET "DISPLAY1<5>"       LOC = "D10";
+NET "DISPLAY1<6>"       LOC = "C10";
+
+NET "DISPLAY2<0>"       LOC = "B9";
+NET "DISPLAY2<1>"       LOC = "A8";
+NET "DISPLAY2<2>"       LOC = "B8";
+NET "DISPLAY2<3>"       LOC = "E7";
+NET "DISPLAY2<4>"       LOC = "E8";
+NET "DISPLAY2<5>"       LOC = "E10";
+NET "DISPLAY2<6>"       LOC = "E9";
+

diff --git a/openMSP430_fpga.vhd b/openMSP430_fpga.vhd
new file mode 100644 (file)
index 0000000..efac81e
--- /dev/null
+++ b/openMSP430_fpga.vhd
@@ -0,0 +1,262 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity openMSP430_fpga is
+  port (
+    CLK_24MHz: in std_logic;
+    RESET: in std_logic;
+    DISPLAY1: out std_logic_vector(6 downto 0);
+    DISPLAY2: out std_logic_vector(6 downto 0)
+  );
+end openMSP430_fpga;
+
+--------------------------------------------------------------------------------
+
+architecture rtl of openMSP430_fpga is
+  component openMSP430 is
+    port(  
+      aclk_en       :  out std_logic;                        -- ACLK enable
+      dbg_freeze    :  out std_logic;                        -- Freeze peripherals
+      dbg_uart_txd  :  out std_logic;                        -- Debug interface: UART TXD
+      dmem_addr     :  out std_logic_vector (8  downto 0);   -- Data Memory address
+      dmem_cen      :  out std_logic;                        -- Data Memory chip enable (low active)
+      dmem_din      :  out std_logic_vector (15 downto 0);   -- Data Memory data input
+      dmem_wen      :  out std_logic_vector (1  downto 0);   -- Data Memory write enable (low active)
+      irq_acc       :  out std_logic_vector (13 downto 0);   -- Interrupt request accepted (one-hot signal)
+      mclk          :  out std_logic;                        -- Main system clock
+      per_addr      :  out std_logic_vector (7  downto 0);   -- Peripheral address
+      per_din       :  out std_logic_vector (15 downto 0);   -- Peripheral data input
+      per_wen       :  out std_logic_vector (1  downto 0);   -- Peripheral write enable (high active)
+      per_en        :  out std_logic;                        -- Peripheral enable (high active)
+      pmem_addr     :  out std_logic_vector (10 downto 0);   -- Program Memory address
+      pmem_cen      :  out std_logic;                        -- Program Memory chip enable (low active)
+      pmem_din      :  out std_logic_vector (15 downto 0);   -- Program Memory data input (optional)
+      pmem_wen      :  out std_logic_vector (1  downto 0);   -- Program Memory write enable (low active) (optional)
+      puc           :  out std_logic;                        -- Main system reset
+      smclk_en      :  out std_logic;                        -- SMCLK enable
+
+      dbg_uart_rxd  :  in  std_logic;                        -- Debug interface: UART RXD
+      dco_clk       :  in  std_logic;                        -- Fast oscillator (fast clock)
+      dmem_dout     :  in  std_logic_vector (15 downto 0);   -- Data Memory data output
+      irq           :  in  std_logic_vector (13 downto 0);   -- Maskable interrupts
+      lfxt_clk      :  in  std_logic;                        -- Low frequency oscillator (typ 32kHz)
+      nmi           :  in  std_logic;                        -- Non-maskable interrupt (asynchronous)
+      per_dout      :  in  std_logic_vector (15 downto 0);   -- Peripheral data output
+      pmem_dout     :  in  std_logic_vector (15 downto 0);   -- Program Memory data output
+      reset_n       :  in  std_logic                         -- Reset Pin (low active)
+    );
+  end component;
+
+  component ram_8x512
+    port (
+      addr: in std_logic_VECTOR(8 downto 0);
+      clk: in std_logic;
+      din: in std_logic_VECTOR(7 downto 0);
+      dout: out std_logic_VECTOR(7 downto 0);
+      en: in std_logic;
+      we: in std_logic
+    );
+  end component;
+  
+  component rom_8x2k
+    port (
+      addr: in std_logic_VECTOR(10 downto 0);
+      clk: in std_logic;
+      din: in std_logic_VECTOR(7 downto 0);
+      dout: out std_logic_VECTOR(7 downto 0);
+      en: in std_logic;
+      we: in std_logic
+    );
+  end component;
+
+
+  component omsp_gpio
+    generic (
+      P1_EN : std_logic;
+      P2_EN : std_logic;
+      P3_EN : std_logic;
+      P4_EN : std_logic;
+      P5_EN : std_logic;
+      P6_EN : std_logic
+    );
+    port(
+      mclk : in std_logic;
+      p1_din : in std_logic_vector(7 downto 0);
+      p2_din : in std_logic_vector(7 downto 0);
+      p3_din : in std_logic_vector(7 downto 0);
+      p4_din : in std_logic_vector(7 downto 0);
+      p5_din : in std_logic_vector(7 downto 0);
+      p6_din : in std_logic_vector(7 downto 0);
+      per_addr : in std_logic_vector(7 downto 0);
+      per_din : in std_logic_vector(15 downto 0);
+      per_en : in std_logic;
+      per_wen : in std_logic_vector(1 downto 0);
+      puc : in std_logic;          
+      irq_port1 : out std_logic;
+      irq_port2 : out std_logic;
+      p1_dout : out std_logic_vector(7 downto 0);
+      p1_dout_en : out std_logic_vector(7 downto 0);
+      p1_sel : out std_logic_vector(7 downto 0);
+      p2_dout : out std_logic_vector(7 downto 0);
+      p2_dout_en : out std_logic_vector(7 downto 0);
+      p2_sel : out std_logic_vector(7 downto 0);
+      p3_dout : out std_logic_vector(7 downto 0);
+      p3_dout_en : out std_logic_vector(7 downto 0);
+      p3_sel : out std_logic_vector(7 downto 0);
+      p4_dout : out std_logic_vector(7 downto 0);
+      p4_dout_en : out std_logic_vector(7 downto 0);
+      p4_sel : out std_logic_vector(7 downto 0);
+      p5_dout : out std_logic_vector(7 downto 0);
+      p5_dout_en : out std_logic_vector(7 downto 0);
+      p5_sel : out std_logic_vector(7 downto 0);
+      p6_dout : out std_logic_vector(7 downto 0);
+      p6_dout_en : out std_logic_vector(7 downto 0);
+      p6_sel : out std_logic_vector(7 downto 0);
+      per_dout : out std_logic_vector(15 downto 0)
+    );
+  end component;
+
+
+  signal mclk : std_logic;
+  signal puc : std_logic;
+
+  signal pmem_addr : std_logic_vector (10 downto 0);
+  signal pmem_dout : std_logic_vector (15 downto 0);
+  signal pmem_cen   : std_logic;
+
+  signal dmem_addr : std_logic_vector (8 downto 0);
+  signal dmem_cen  : std_logic;
+  signal dmem_wen  : std_logic_vector (1  downto 0);
+  signal dmem_din  : std_logic_vector (15 downto 0);
+  signal dmem_dout : std_logic_vector (15 downto 0);
+  
+  signal per_din : std_logic_vector (15 downto 0);
+  signal per_dout : std_logic_Vector (15 downto 0);
+  signal per_wen : std_logic_vector (1 downto 0);
+  signal per_en : std_logic;
+  signal per_addr : std_logic_vector (7 downto 0);
+
+--------------------------------------------------------------------------------
+
+begin
+  openMSP430_0 : openMSP430 port map (
+    aclk_en       => open,
+    dbg_freeze    => open,
+    dbg_uart_txd  => open,
+    dmem_addr     => dmem_addr,
+    dmem_cen      => dmem_cen,
+    dmem_din      => dmem_din,
+    dmem_wen      => dmem_wen,
+    irq_acc       => open,
+    mclk          => mclk,
+    per_addr      => per_addr,
+    per_din       => per_din,
+    per_wen       => per_wen,
+    per_en        => per_en,
+    pmem_addr     => pmem_addr,
+    pmem_cen      => pmem_cen,
+    pmem_din      => open,
+    pmem_wen      => open,
+    puc           => puc,
+    smclk_en      => open,
+  
+    dbg_uart_rxd  => '0',
+    dco_clk       => CLK_24MHz,
+    dmem_dout     => dmem_dout,
+    irq           => (others => '0'),
+    lfxt_clk      => '0',
+    nmi           => '0',
+    per_dout      => per_dout,
+    pmem_dout     => pmem_dout,
+    reset_n       => RESET
+  );
+
+  ram_8x512_hi : ram_8x512 port map (
+    addr => dmem_addr,
+    clk => mclk,
+    din => dmem_din (15 downto 8),
+    dout => dmem_dout (15 downto 8),
+    en => dmem_cen,
+    we => dmem_wen (1)
+  );
+  
+  ram_8x512_lo : ram_8x512 port map (
+    addr => dmem_addr,
+    clk => mclk,
+    din => dmem_din (7 downto 0),
+    dout => dmem_dout (7 downto 0),
+    en => dmem_cen,
+    we => dmem_wen (0)
+  );
+  
+  rom_8x2k_hi : rom_8x2k port map (
+    addr => pmem_addr,
+    clk => mclk,
+    din => (others => '0'),
+    dout => pmem_dout (15 downto 8),
+    en => pmem_cen,
+    we => '1'
+  );
+      
+  rom_8x2k_lo : rom_8x2k port map (
+    addr => pmem_addr,
+    clk => mclk,
+    din => (others => '0'),
+    dout => pmem_dout (7 downto 0),
+    en => pmem_cen,
+    we => '1'
+  );
+
+
+  omsp_gpio_0 : omsp_gpio
+    generic map (
+      P1_EN => '1',  -- Enable Port 1
+      P2_EN => '1',  -- Enable Port 2
+      P3_EN => '0',  -- Enable Port 3
+      P4_EN => '0',  -- Enable Port 4
+      P5_EN => '0',  -- Enable Port 5
+      P6_EN => '0'   -- Enable Port 6
+    )
+    port map (
+      irq_port1 => open,
+      irq_port2 => open,
+      p1_dout (6 downto 0) => DISPLAY1,
+      p1_dout (7) => open,
+      p1_dout_en => open,
+      p1_sel => open,
+      p2_dout (6 downto 0) => DISPLAY2,
+      p2_dout (7) => open,
+      p2_dout_en => open,
+      p2_sel => open,
+      p3_dout => open,
+      p3_dout_en => open,
+      p3_sel => open,
+      p4_dout => open,
+      p4_dout_en => open,
+      p4_sel => open,
+      p5_dout => open,
+      p5_dout_en => open,
+      p5_sel => open,
+      p6_dout => open,
+      p6_dout_en => open,
+      p6_sel => open,
+      per_dout => per_dout,
+      mclk => mclk,
+      p1_din => (others => '0'),
+      p2_din => (others => '0'),
+      p3_din => (others => '0'),
+      p4_din => (others => '0'),
+      p5_din => (others => '0'),
+      p6_din => (others => '0'),
+      per_addr => per_addr,
+      per_din => per_din,
+      per_en => per_en,
+      per_wen => per_wen,
+      puc => puc
+    );
+
+  
+end rtl;
+