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+ Top level design
[fpga/virtex2/blink.git] / openMSP430_fpga.prj
1 verilog work openmsp430/omsp_alu.v
2 verilog work openmsp430/omsp_clock_module.v
3 verilog work openmsp430/omsp_dbg.v
4 verilog work openmsp430/omsp_dbg_hwbrk.v
5 verilog work openmsp430/omsp_dbg_uart.v
6 verilog work openmsp430/omsp_execution_unit.v
7 verilog work openmsp430/omsp_frontend.v
8 verilog work openmsp430/omsp_mem_backbone.v
9 verilog work openmsp430/omsp_multiplier.v
10 verilog work openmsp430/omsp_register_file.v
11 verilog work openmsp430/omsp_sfr.v
12 verilog work openmsp430/omsp_watchdog.v
13 verilog work openmsp430/openMSP430.v
14 verilog work openmsp430/openMSP430_undefines.v
15 verilog work openmsp430/timescale.v
16
17 verilog work openMSP430_defines.v
18
19 verilog work openmsp430/periph/omsp_gpio.v
20 verilog work openmsp430/periph/omsp_timerA.v
21
22 vhdl work coregen/ram_8x512.vhd
23 vhdl work coregen/rom_8x2k.vhd
24
25 vhdl work openMSP430_fpga.vhd
26