Resets changed from asynchronous to synchronous.

[fpga/uart.git] / uart.vhd

diff --git a/uart.vhd b/uart.vhd
index 11eb9b243eae781c3ff2992d55ed25dd411ab510..da189c487fe6fd12e3d6f496011b35fbc79b79c6 100644 (file)
--- a/uart.vhd
+++ b/uart.vhd
@@ -129,9 +129,9 @@ architecture dataflow of uart is
   signal reg_re_b : boolean_vector (512 downto 0);
 
   
-  signal reg_baud : std_logic_vector (15 downto 0) := "0000000000000010";
+  signal reg_baud : std_logic_vector (15 downto 0) := (others => '0');
   signal reg_stat : std_logic_vector (7 downto 0);
-  signal reg_ie   : std_logic_vector (7 downto 0);
+  signal reg_ie   : std_logic_vector (7 downto 0) := (others => '0');
 
   
   signal tx_clk        : std_logic;
@@ -284,21 +284,23 @@ begin
   
   process (mclk, puc) is
   begin
-    if puc = '1' then
-      reg_baud <= (others => '0');
-      reg_ie   <= (others => '0');
-      
-    elsif mclk'event and mclk = '1' then
-      if reg_we (UBAUD) = '1' then
-        reg_baud (7 downto 0) <= per_din_low;
-      end if;
+    if mclk'event and mclk = '1' then
+      if puc = '1' then
+        reg_baud <= (others => '0');
+        reg_ie   <= (others => '0');
+
+      else
+        if reg_we (UBAUD) = '1' then
+          reg_baud (7 downto 0) <= per_din_low;
+        end if;
 
-      if reg_we (UBAUD+1) = '1' then
-        reg_baud (15 downto 8) <= per_din_high;
-      end if;
+        if reg_we (UBAUD+1) = '1' then
+          reg_baud (15 downto 8) <= per_din_high;
+        end if;
 
-      if reg_we (USTAT) = '1' then
-        reg_ie <= per_din_low;
+        if reg_we (USTAT) = '1' then
+          reg_ie <= per_din_low;
+        end if;
       end if;
     end if;
   end process;