Early initialization of all relevant signals.

[fpga/uart.git] / uart.vhd

diff --git a/uart.vhd b/uart.vhd
index 11eb9b243eae781c3ff2992d55ed25dd411ab510..09450f91f1bc0ada7428853220b7ad17ca45573b 100644 (file)
--- a/uart.vhd
+++ b/uart.vhd
@@ -129,9 +129,9 @@ architecture dataflow of uart is
   signal reg_re_b : boolean_vector (512 downto 0);
 
   
-  signal reg_baud : std_logic_vector (15 downto 0) := "0000000000000010";
+  signal reg_baud : std_logic_vector (15 downto 0) := (others => '0');
   signal reg_stat : std_logic_vector (7 downto 0);
-  signal reg_ie   : std_logic_vector (7 downto 0);
+  signal reg_ie   : std_logic_vector (7 downto 0) := (others => '0');
 
   
   signal tx_clk        : std_logic;