X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/uart.git/blobdiff_plain/81d30909cb24a0f382a045c90f11444dd35cc1cf..6ce709d167d1e0f4b0ab62ad931b737ea781136a:/uart.vhd

diff --git a/uart.vhd b/uart.vhd
index 11eb9b2..09450f9 100644
--- a/uart.vhd
+++ b/uart.vhd
@@ -129,9 +129,9 @@ architecture dataflow of uart is
   signal reg_re_b : boolean_vector (512 downto 0);
 
   
-  signal reg_baud : std_logic_vector (15 downto 0) := "0000000000000010";
+  signal reg_baud : std_logic_vector (15 downto 0) := (others => '0');
   signal reg_stat : std_logic_vector (7 downto 0);
-  signal reg_ie   : std_logic_vector (7 downto 0);
+  signal reg_ie   : std_logic_vector (7 downto 0) := (others => '0');
 
   
   signal tx_clk        : std_logic;