Resets changed from asynchronous to synchronous.

[fpga/uart.git] / baud_gen.vhd

diff --git a/baud_gen.vhd b/baud_gen.vhd
index f3312f0c66cd0df1b75980ecbcc71339dc6ccc8b..b752d08a612acb81db515af8508790d274beaed1 100644 (file)
--- a/baud_gen.vhd
+++ b/baud_gen.vhd
@@ -56,22 +56,24 @@ begin
 
   process (clk, reset)
   begin
-    if (reset = '1') then
-      counter <= (others => '0');
-      clk_baud_s <= '0';
-      
-    elsif (rising_edge(clk)) then
-      if (clk_baud_s = '0' and ce = '0') then
+    if (rising_edge(clk)) then
+      if (reset = '1') then
         counter <= (others => '0');
+        clk_baud_s <= '0';
 
       else
-        if (counter = 0) then
-          counter    <= scale;
-          clk_baud_s <= not clk_baud_s;
+        if (clk_baud_s = '0' and ce = '0') then
+          counter <= (others => '0');
 
         else
-          counter <= counter - 1;
+          if (counter = 0) then
+            counter    <= scale;
+            clk_baud_s <= not clk_baud_s;
 
+          else
+            counter <= counter - 1;
+
+          end if;
         end if;
       end if;
     end if;