use work.dff.all;
entity qcounter is
- port (
- clock: in std_logic;
- reset: in std_logic;
- a0, b0: in std_logic;
- qcount: out std_logic_vector (31 downto 0);
- a_rise, a_fall, b_rise, b_fall, ab_event: out std_logic;
- ab_error: out std_logic
- );
+port (
+ clock: in std_logic;
+ reset: in std_logic;
+ a0, b0: in std_logic;
+ qcount: out std_logic_vector (31 downto 0);
+ a_rise, a_fall, b_rise, b_fall, ab_event: out std_logic;
+ ab_error: out std_logic
+);
end qcounter;
architecture behavioral of qcounter is
- component dff
- port (
- clock: in std_logic;
- d: in std_logic;
- q: out std_logic
- );
- end component;
+ component dff
+ port (
+ clock: in std_logic;
+ d: in std_logic;
+ q: out std_logic
+ );
+ end component;
-subtype std_logic4 is std_logic_vector (3 downto 0);
- signal a, b, a_prev, b_prev: std_logic;
- signal count_prev: std_logic_vector (29 downto 0)
- := "000000000000000000000000000000";
- signal count: std_logic_vector (29 downto 0);
+ subtype std_logic4 is std_logic_vector (3 downto 0);
+ signal a, b, a_prev, b_prev: std_logic;
+ signal count_prev: std_logic_vector (29 downto 0)
+ := "000000000000000000000000000000";
+ signal count: std_logic_vector (29 downto 0);
begin
- dff_a: dff
- port map (
- clock => clock,
- d => a0,
- q => a
- );
- dff_b: dff
- port map (
- clock => clock,
- d => b0,
- q => b
- );
+ dff_a: dff
+ port map (
+ clock => clock,
+ d => a0,
+ q => a
+ );
+
+ dff_b: dff
+ port map (
+ clock => clock,
+ d => b0,
+ q => b
+ );
- qcount(0) <= a xor b;
- qcount(1) <= b;
- qcount(31 downto 2) <= count;
+ qcount(0) <= a xor b;
+ qcount(1) <= b;
+ qcount(31 downto 2) <= count;
- comb_event: process (a_prev, b_prev, a, b)
- begin
- a_rise <= '0';
- a_fall <= '0';
- b_rise <= '0';
- b_fall <= '0';
- ab_event <= '0';
- ab_error <= '0';
- if ((a xor a_prev) and (b xor b_prev)) = '1' then
- -- forbidden double transition
- ab_error <= '1';
- else
- a_rise <= (a xor a_prev) and a;
- a_fall <= (a xor a_prev) and not a;
- b_rise <= (b xor b_prev) and b;
- b_fall <= (b xor b_prev) and not b;
- ab_event <= (a xor a_prev) or (b xor b_prev);
- end if;
- end process;
+ comb_event: process (a_prev, b_prev, a, b)
+ begin
+ a_rise <= '0';
+ a_fall <= '0';
+ b_rise <= '0';
+ b_fall <= '0';
+ ab_event <= '0';
+ ab_error <= '0';
+ if ((a xor a_prev) and (b xor b_prev)) = '1' then
+ -- forbidden double transition
+ ab_error <= '1';
+ else
+ a_rise <= (a xor a_prev) and a;
+ a_fall <= (a xor a_prev) and not a;
+ b_rise <= (b xor b_prev) and b;
+ b_fall <= (b xor b_prev) and not b;
+ ab_event <= (a xor a_prev) or (b xor b_prev);
+ end if;
+ end process;
- comb_count: process (a_prev, b_prev, a, b, count)
- begin
- if (a_prev = '0') and (b_prev = '1') and (a = '0') and (b = '0') then
- count <= count_prev + 1;
- elsif (a_prev = '0') and (b_prev = '0') and (a = '0') and (b = '1') then
- count <= count_prev - 1;
- else
- count <= count_prev;
- end if;
- end process;
-
- seq: process
- begin
- wait until clock'event and clock = '1';
- if reset = '1' then
- count_prev <= "000000000000000000000000000000";
- else
- count_prev <= count;
- end if;
- a_prev <= a;
- b_prev <= b;
- end process;
+ comb_count: process (a_prev, b_prev, a, b, count)
+ begin
+ if (a_prev = '0') and (b_prev = '1') and (a = '0') and (b = '0') then
+ count <= count_prev + 1;
+ elsif (a_prev = '0') and (b_prev = '0') and (a = '0') and (b = '1') then
+ count <= count_prev - 1;
+ else
+ count <= count_prev;
+ end if;
+ end process;
+ seq: process
+ begin
+ wait until clock'event and clock = '1';
+ if reset = '1' then
+ count_prev <= "000000000000000000000000000000";
+ else
+ count_prev <= count;
+ end if;
+ a_prev <= a;
+ b_prev <= b;
+ end process;
+
end behavioral;
use work.qcounter.all;
entity rpi_mc_simple_dc is
- port (
- gpio2: in std_logic; -- SDA
- gpio3: in std_logic; -- SCL
- gpio4: in std_logic; -- CLK
- gpio14: in std_logic; -- Tx
- gpio15: in std_logic; -- Rx
- gpio17: out std_logic; -- RTS
- gpio18: out std_logic; -- PWM0/PCMCLK
- gpio27: out std_logic; -- SD1DAT3
- gpio22: out std_logic; -- SD1CLK
- gpio23: out std_logic; -- SD1CMD
- gpio24: out std_logic; -- SD1DAT0
- gpio10: in std_logic; -- SPI0MOSI
- gpio9: out std_logic; -- SPI0MISO
- gpio25: out std_logic; -- SD1DAT1
- gpio11: in std_logic; -- SPI0SCLK
- gpio8: in std_logic; -- SPI0CE0
- gpio7: in std_logic; -- SPI0CE1
- gpio5: in std_logic; -- GPCLK1
- gpio6: in std_logic; -- GPCLK2
- gpio12: in std_logic; -- PWM0
- gpio13: in std_logic; -- PWM1
- gpio19: in std_logic; -- PWM1/SPI1MISO/PCMFS
- gpio16: in std_logic; -- SPI1CE2
- gpio26: in std_logic; -- SD1DAT2
- gpio20: in std_logic; -- SPI1MOSI/PCMDIN/GPCLK0
- gpio21: in std_logic; -- SPI1SCLK/PCMDOUT/GPCLK1
- --
- -- PWM
- -- Each PWM signal has cooresponding shutdown
- pwm: out std_logic_vector (1 to 3);
- shdn: out std_logic_vector (1 to 3);
- -- Fault/power stage status
- stat: in std_logic_vector (1 to 3);
- -- HAL inputs
- hal_in: in std_logic_vector (1 to 3);
- -- IRC inputs
- irc_a: in std_logic;
- irc_b: in std_logic;
- irc_i: in std_logic;
- -- Power status
- power_stat: in std_logic;
- -- ADC for current
- adc_miso: in std_logic;
- adc_mosi: in std_logic;
- adc_sclk: in std_logic;
- adc_scs: in std_logic;
- -- Extarnal SPI
- ext_miso: in std_logic; --master in slave out
- ext_mosi: in std_logic; --master out slave in
- ext_sclk: in std_logic;
- ext_scs0: in std_logic;
- ext_scs1: in std_logic;
- ext_scs2: in std_logic;
- -- RS-485 Transceiver
- rs485_rxd: in std_logic;
- rs485_txd: out std_logic;
- rs485_dir: out std_logic;
- -- CAN Transceiver
- can_rx: in std_logic;
- can_tx: in std_logic;
- -- DIP switch
- dip_sw: in std_logic_vector (1 to 3); --na desce je prohozene cislovanni
- -- Unused terminal to keep design tools silent
- dummy_unused : out std_logic
- );
+port (
+ gpio2: in std_logic; -- SDA
+ gpio3: in std_logic; -- SCL
+ gpio4: in std_logic; -- CLK
+ gpio14: in std_logic; -- Tx
+ gpio15: in std_logic; -- Rx
+ gpio17: out std_logic; -- RTS
+ gpio18: out std_logic; -- PWM0/PCMCLK
+ gpio27: out std_logic; -- SD1DAT3
+ gpio22: out std_logic; -- SD1CLK
+ gpio23: out std_logic; -- SD1CMD
+ gpio24: out std_logic; -- SD1DAT0
+ gpio10: in std_logic; -- SPI0MOSI
+ gpio9: out std_logic; -- SPI0MISO
+ gpio25: out std_logic; -- SD1DAT1
+ gpio11: in std_logic; -- SPI0SCLK
+ gpio8: in std_logic; -- SPI0CE0
+ gpio7: in std_logic; -- SPI0CE1
+ gpio5: in std_logic; -- GPCLK1
+ gpio6: in std_logic; -- GPCLK2
+ gpio12: in std_logic; -- PWM0
+ gpio13: in std_logic; -- PWM1
+ gpio19: in std_logic; -- PWM1/SPI1MISO/PCMFS
+ gpio16: in std_logic; -- SPI1CE2
+ gpio26: in std_logic; -- SD1DAT2
+ gpio20: in std_logic; -- SPI1MOSI/PCMDIN/GPCLK0
+ gpio21: in std_logic; -- SPI1SCLK/PCMDOUT/GPCLK1
+ --
+ -- PWM
+ -- Each PWM signal has cooresponding shutdown
+ pwm: out std_logic_vector (1 to 3);
+ shdn: out std_logic_vector (1 to 3);
+ -- Fault/power stage status
+ stat: in std_logic_vector (1 to 3);
+ -- HAL inputs
+ hal_in: in std_logic_vector (1 to 3);
+ -- IRC inputs
+ irc_a: in std_logic;
+ irc_b: in std_logic;
+ irc_i: in std_logic;
+ -- Power status
+ power_stat: in std_logic;
+ -- ADC for current
+ adc_miso: in std_logic;
+ adc_mosi: in std_logic;
+ adc_sclk: in std_logic;
+ adc_scs: in std_logic;
+ -- Extarnal SPI
+ ext_miso: in std_logic; --master in slave out
+ ext_mosi: in std_logic; --master out slave in
+ ext_sclk: in std_logic;
+ ext_scs0: in std_logic;
+ ext_scs1: in std_logic;
+ ext_scs2: in std_logic;
+ -- RS-485 Transceiver
+ rs485_rxd: in std_logic;
+ rs485_txd: out std_logic;
+ rs485_dir: out std_logic;
+ -- CAN Transceiver
+ can_rx: in std_logic;
+ can_tx: in std_logic;
+ -- DIP switch
+ dip_sw: in std_logic_vector (1 to 3); --na desce je prohozene cislovanni
+ -- Unused terminal to keep design tools silent
+ dummy_unused : out std_logic
+);
end rpi_mc_simple_dc;
projects / fpga / rpi-motor-control.git / commitdiff