signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin
signal pwm_in, pwm_dir_in: std_logic;
- signal spi_clk: std_logic;
signal gpio_clk: std_logic;
signal dat_reg : STD_LOGIC_VECTOR (95 downto 0); --shift register for spi
signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
begin
-- PLL as a reset generator
- --zesileni signalu hodin SPI - bez zesileni nelze syntetizovat
- copyclk: CLKINT
- port map (
- a => gpio11,
- y => spi_clk
- );
-
--zesileni signalu GPIO CLK
copyclk2: CLKINT
port map (
--position is obtained on rising edge -> we should write it on falling edge
wait until (gpio_clk'event and gpio_clk='0');
- spiclk_old(0)<=spi_clk;
+ --SCLK edge detection
+ spiclk_old(0)<=gpio11;
spiclk_old(1)<=spiclk_old(0);
+ --SS edge detection
ce0_old(0)<=gpio7;
ce0_old(1)<=ce0_old(0);