Include in PMSM design to implement safe behavior when external clocks are not present.
authorPavel Pisa <ppisa@pikron.com>
Fri, 1 May 2015 14:59:49 +0000 (16:59 +0200)
committerPavel Pisa <ppisa@pikron.com>
Fri, 1 May 2015 14:59:49 +0000 (16:59 +0200)
commit24df44d1c49bcb0f29f43f577ef3d245bced9e28
tree720de7b3a903c3d78c152171714bf610743eb562
parent87d07bcf7cedbfe9633a7c3b3e129a3bee8e6968
Include in PMSM design to implement safe behavior when external clocks are not present.

The PLL is configured to synthesize 200 MHz clock from 50 MHz input.
The clock monitor holds PWM outputs low if the external clocks are
not present. The reference lost is recognized 6 in 8 cycles
of 200 MHz synthesized clock as well.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
pmsm-control/pll50to200.vhd [new file with mode: 0644]
pmsm-control/rpi_pmsm_control.sdc [new file with mode: 0644]
pmsm-control/rpi_pmsm_control.vhdl