+ if (data_ready='1') then
+ --add the current current to sum and shift the register
+ cumul_data(71 downto 0)<=
+ std_logic_vector(unsigned(cumul_data(47 downto 24))
+ +unsigned(adc_data(11 downto 0)))
+ & cumul_data(23 downto 0)
+ & cumul_data(71 downto 48);
+ end if;
+ state<=f8;
+ when f8=> --8th falling edge
+ adc_sclk<='0';
+ adc_mosi<='0'; --PD0