Simple frequency divider replaced with more complex counter.

[fpga/rpi-motor-control.git] / pmsm-control / rpi_pmsm_control.vhdl

diff --git a/pmsm-control/rpi_pmsm_control.vhdl b/pmsm-control/rpi_pmsm_control.vhdl
index 27ca4d849075ce817c4efb54bdffa2af8510cfa8..13ffb97cda27f6aae95c4f46c00f45b6c5100fe6 100644 (file)
--- a/pmsm-control/rpi_pmsm_control.vhdl
+++ b/pmsm-control/rpi_pmsm_control.vhdl
@@ -144,10 +144,17 @@ architecture behavioral of rpi_pmsm_control is
        end component;
        
        --frequency division by 12
-       component divider is
-       port (
-               clk_in: in std_logic;
-               div12: out std_logic
+       component cnt_div is
+       generic (
+               cnt_width_g : natural := 4
+       );
+       port
+       (
+               clk_i     : in std_logic;                               --clk to divide
+               en_i      : in std_logic;                               --enable bit?
+               reset_i   : in std_logic;                               --asynch. reset
+               ratio_i   : in std_logic_vector(cnt_width_g-1 downto 0);--initial value
+               q_out_o   : out std_logic                               --generates puls when counter underflows
        );
        end component;
        
@@ -197,6 +204,7 @@ architecture behavioral of rpi_pmsm_control is
        
        signal pwm_match: pwm_res_type;                                 --point of reversion of pwm output, 0 to 2047
        signal pwm_count: std_logic_vector (pwm_width-1 downto 0);      --counter, 0 to 2047
+       signal pwm_sync_at_next: std_logic;
        signal pwm_sync: std_logic;
        signal pwm_en_p: std_logic_vector(1 to 3);
        signal pwm_en_n: std_logic_vector(1 to 3);
@@ -261,7 +269,7 @@ begin
                port map (
                        clock => gpio_clk,                              --50 Mhz clk from gpclk on raspberry
                        sync => pwm_sync,                               --counter restarts
-                       data_valid => income_data_valid,                        
+                       data_valid => pwm_sync_at_next,                 
                        failsafe => failsafe,
                        --
                        -- pwm config bits & match word
@@ -277,11 +285,13 @@ begin
        end generate;
        
        
-       div12_map: divider
+       div12_map: cnt_div
        port map(
-               --reset => income_data_valid,
-               clk_in => gpio_clk,
-               div12 => clk_4M17
+               clk_i  => gpio_clk,
+               en_i   =>'1',
+               reset_i   =>'0',
+               ratio_i   =>"1101", --POZN.: counter detekuje cnt<=1
+               q_out_o   =>clk_4M17
        );
        
        -- ADC needs 3.2 MHz clk when powered from +5V Vcc
@@ -344,8 +354,16 @@ begin
        process
        begin
                wait until (gpio_clk'event and gpio_clk='1');
-               IF(pwm_count = pwm_period) THEN                         
-               --end of period reached
+               IF pwm_count = std_logic_vector(unsigned(pwm_period) - 1) THEN                          
+                       --end of period nearly reached
+                       --fetch new pwm match data
+                       pwm_sync_at_next <= '1';
+               else
+                       pwm_sync_at_next <= '0';
+               end if;
+               
+               if pwm_sync_at_next='1' then
+                       --end of period reached
                        pwm_count <= (others=>'0');      --reset counter
                        pwm_sync <= '1';                                -- inform PWM logic about new period start
                ELSE                                                    --end of period not reached