signal prepared_data: std_logic_vector(71 downto 0); --consistent data, waiting for clk sync to propagate to output
signal m_count_sig: std_logic_vector(8 downto 0); --measurments count waiting for clk to propagate to output
signal first_pass: std_logic;
- signal div_clk_prev: std_logic;
begin
reset_re:='1';
end if;
- --rising edge detection of divided clk signal
- div_clk_prev<=divided_clk;
- if (divided_clk='1') and (div_clk_prev='0') then
+ if (divided_clk='1') then --instead of divide, single puls is now detected
case state is
when reset=>
--- /dev/null
+--
+-- * Counter - divider *
+--
+-- part of LXPWR motion control board (c) PiKRON Ltd
+-- idea by Pavel Pisa PiKRON Ltd <ppisa@pikron.com>
+--
+-- license: BSD
+--
+-- This file is used in "RPI PMS motor control" as frequency divider - divides by 6
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity cnt_div is
+ generic (
+ cnt_width_g : natural := 4
+ );
+ port
+ (
+ clk_i : in std_logic; --clk to divide
+ en_i : in std_logic; --enable bit?
+ reset_i : in std_logic; --asynch. reset
+ ratio_i : in std_logic_vector(cnt_width_g-1 downto 0);--initial value
+ q_out_o : out std_logic --generates puls when counter underflows
+ );
+end cnt_div;
+
+architecture behavioral of cnt_div is
+ signal cnt_val_s : natural range 0 to (2**cnt_width_g - 1); --counter value before DFF
+ signal cnt_val_r : natural range 0 to (2**cnt_width_g - 1); --counter value after DFF
+begin
+
+comb: process (reset_i, en_i, ratio_i, cnt_val_r)
+ begin
+ if reset_i = '1' then --reset detection
+ cnt_val_s <= to_integer(unsigned(ratio_i)); --set initial value
+ q_out_o <= '0'; --reset output
+ else
+ if en_i = '0' then --stop-state
+ cnt_val_s <= cnt_val_r; --hold the value
+ q_out_o <= '0'; --reset output
+ else
+ if cnt_val_r <= 1 then --counter underflows
+ cnt_val_s <= to_integer(unsigned(ratio_i)); --set initial value
+ q_out_o <= '1'; --set output
+ else
+ cnt_val_s <= cnt_val_r - 1; --decrement counter
+ q_out_o <= '0'; --reset output
+ end if;
+ end if;
+ end if;
+ end process;
+
+seq: process
+ begin
+ wait until clk_i'event and clk_i = '1';
+ cnt_val_r <= cnt_val_s;
+ end process;
+
+end behavioral;
+
+++ /dev/null
--- provides frequency division by 12
--- initialy intended to make 4.17Mhz from 50Mhz
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.util.all;
-
-entity divider is
-
-port (
- clk_in: in std_logic;
- div12: out std_logic
-);
-end divider;
-
-
-architecture behavioral of divider is
- signal count : std_logic_vector (2 downto 0);
- signal tmp : std_logic;
-begin
-
-
- divider : process
- begin
- wait until (clk_in'event and clk_in='1');
- if (count(2 downto 1)="11") then
- count<="000";
- tmp <= not tmp;
- else
- count <= std_logic_vector(unsigned(count) + 1);
- end if;
- div12<=tmp;
- end process divider;
-
-
-
-end behavioral;
-
end component;
--frequency division by 12
- component divider is
- port (
- clk_in: in std_logic;
- div12: out std_logic
+ component cnt_div is
+ generic (
+ cnt_width_g : natural := 4
+ );
+ port
+ (
+ clk_i : in std_logic; --clk to divide
+ en_i : in std_logic; --enable bit?
+ reset_i : in std_logic; --asynch. reset
+ ratio_i : in std_logic_vector(cnt_width_g-1 downto 0);--initial value
+ q_out_o : out std_logic --generates puls when counter underflows
);
end component;
end generate;
- div12_map: divider
+ div12_map: cnt_div
port map(
- --reset => income_data_valid,
- clk_in => gpio_clk,
- div12 => clk_4M17
+ clk_i => gpio_clk,
+ en_i =>'1',
+ reset_i =>'0',
+ ratio_i =>"1101", --POZN.: counter detekuje cnt<=1
+ q_out_o =>clk_4M17
);
-- ADC needs 3.2 MHz clk when powered from +5V Vcc