end component;
--frequency division by 12
- component divider is
- port (
- clk_in: in std_logic;
- div12: out std_logic
+ component cnt_div is
+ generic (
+ cnt_width_g : natural := 4
+ );
+ port
+ (
+ clk_i : in std_logic; --clk to divide
+ en_i : in std_logic; --enable bit?
+ reset_i : in std_logic; --asynch. reset
+ ratio_i : in std_logic_vector(cnt_width_g-1 downto 0);--initial value
+ q_out_o : out std_logic --generates puls when counter underflows
);
end component;
end generate;
- div12_map: divider
+ div12_map: cnt_div
port map(
- --reset => income_data_valid,
- clk_in => gpio_clk,
- div12 => clk_4M17
+ clk_i => gpio_clk,
+ en_i =>'1',
+ reset_i =>'0',
+ ratio_i =>"1101", --POZN.: counter detekuje cnt<=1
+ q_out_o =>clk_4M17
);
-- ADC needs 3.2 MHz clk when powered from +5V Vcc