Include in PMSM design to implement safe behavior when external clocks are not present.

[fpga/rpi-motor-control.git] / pmsm-control / rpi_pmsm_control.vhdl

diff --git a/pmsm-control/rpi_pmsm_control.vhdl b/pmsm-control/rpi_pmsm_control.vhdl
index 4829bebb6b40e8ec6ba7a1b14754352d528de7c1..c3f8416a6210e10c17a7769d19a8f46c68397bfb 100644 (file)
--- a/pmsm-control/rpi_pmsm_control.vhdl
+++ b/pmsm-control/rpi_pmsm_control.vhdl
@@ -93,13 +93,14 @@ architecture behavioral of rpi_pmsm_control is
        attribute syn_preserve :boolean;
        attribute syn_keep :boolean;
        attribute syn_hier :boolean;
        attribute syn_preserve :boolean;
        attribute syn_keep :boolean;
        attribute syn_hier :boolean;

+

        -- Actel lib
        -- Actel lib

-       -- component pll50to200
-       --   port (
-       --     powerdown, clka: in std_logic;
-       --     lock, gla: out std_logic
-       --   );
-       -- end component;
+       component pll50to200
+               port (
+                       powerdown, clka: in std_logic;
+                       lock, gla: out std_logic
+               );
+       end component;

        
        component CLKINT
                port (A: in std_logic; Y: out std_logic);
        
        component CLKINT
                port (A: in std_logic; Y: out std_logic);


@@ -159,10 +160,18 @@ architecture behavioral of rpi_pmsm_control is
        signal adc_reset : std_logic;
        signal adc_channels: std_logic_vector(71 downto 0);
        signal adc_m_count: std_logic_vector(8 downto 0);
        signal adc_reset : std_logic;
        signal adc_channels: std_logic_vector(71 downto 0);
        signal adc_m_count: std_logic_vector(8 downto 0);

-       
+
+       --clock signals for logic and master fail monitoring
+       signal gpio_clk: std_logic;
+       signal pll_clkin, pll_clkout, pll_lock: std_logic;
+       signal clkmon_dly1, clkmon_dly2: std_logic;
+       signal clkmon_fail, clkmon_fail_next: std_logic;
+       signal clkmon_wdg: integer range 0 to 6;
+       signal reset_sync, reset_async: std_logic;
+       signal failsafe, next_failsafe: std_logic;
+

        signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin
        --signal pwm_in, pwm_dir_in: std_logic;
        signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin
        --signal pwm_in, pwm_dir_in: std_logic;

-       signal gpio_clk: std_logic;

        signal dat_reg : STD_LOGIC_VECTOR (127 downto 0); --shift register for spi
        signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
        signal index_position: std_logic_vector(11 downto 0);           --pozice irc_i
        signal dat_reg : STD_LOGIC_VECTOR (127 downto 0); --shift register for spi
        signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
        signal index_position: std_logic_vector(11 downto 0);           --pozice irc_i


@@ -202,6 +211,19 @@ begin
                y => gpio_clk
        );
        
                y => gpio_clk
        );
        

+       pll: pll50to200
+       port map (
+               powerdown => '1',
+               clka => pll_clkin,
+               gla => pll_clkout,
+               lock => pll_lock);
+
+       -- the failasfe signal from communication block if CRC is used
+       next_failsafe <= '0';
+
+       reset_async <= not pll_lock or clkmon_fail;
+
+       pll_clkin <= gpio_clk;

        
        qcount: qcounter
        port map (
        
        qcount: qcounter
        port map (


@@ -227,7 +249,7 @@ begin
                        clock => gpio_clk,                              --50 Mhz clk from gpclk on raspberry
                        sync => pwm_sync,                               --counter restarts
                        data_valid => income_data_valid,                        
                        clock => gpio_clk,                              --50 Mhz clk from gpclk on raspberry
                        sync => pwm_sync,                               --counter restarts
                        data_valid => income_data_valid,                        

-                       failsafe => '0',
+                       failsafe => failsafe,

                        --
                        -- pwm config bits & match word
                        --
                        --
                        -- pwm config bits & match word
                        --


@@ -266,19 +288,6 @@ begin
                
        );
 
                
        );
 

-       
-       
-       --   pll: pll50to200
-       --     port map (
-       --       powerdown => '1',
-       --       clka => pll_clkin,
-       --       gla => pll_clkout,
-       --       lock => pll_lock);
-       -- --  reset <= not pll_lock;
-       --   reset <= '0';                         -- TODO: apply reset for good failsafe
-                                           -- upon power-on
-       --   clock <= clkm;
-

        dummy_unused <= gpio2 and gpio3  and gpio4 and
                gpio5 and gpio6 and
                gpio12 and gpio13 and gpio14 and
        dummy_unused <= gpio2 and gpio3  and gpio4 and
                gpio5 and gpio6 and
                gpio12 and gpio13 and gpio14 and


@@ -372,6 +381,41 @@ begin
                        income_data_valid<='1';
                end if;
        end process;
                        income_data_valid<='1';
                end if;
        end process;

-                       
+
+       clock_monitor: process (pll_clkout, gpio_clk, clkmon_dly1, clkmon_wdg, clkmon_fail_next)
+       begin
+               if pll_clkout'event and pll_clkout = '1' then
+                       clkmon_dly1 <= gpio_clk;
+                       clkmon_dly2 <= clkmon_dly1;
+                       if clkmon_dly1 = '0' and clkmon_dly2 = '1' then
+                               clkmon_wdg <= 6;
+                               clkmon_fail_next <= '0';
+                       elsif clkmon_wdg > 0 then
+                               clkmon_wdg <= clkmon_wdg - 1;
+                               clkmon_fail_next <= '0';
+                       else
+                               clkmon_wdg <= 0;
+                               clkmon_fail_next <= '1';
+                       end if;
+                       clkmon_fail <= clkmon_fail_next;
+               end if;
+       end process;
+
+       async_rst: process (gpio_clk, reset_async, reset_sync)
+       begin
+               if reset_async = '1' then
+                       failsafe <= '1';
+               elsif gpio_clk'event and gpio_clk = '1' then
+                       failsafe <= next_failsafe or reset_sync;
+               end if;
+       end process;
+
+       sync_rst: process (gpio_clk, reset_async)
+       begin
+               if gpio_clk'event and gpio_clk = '1' then
+                       reset_sync <= reset_async;
+               end if;
+       end process;
+

 end behavioral;
 
 end behavioral;