Modified ADC clk frequency from 3.2 MHz to 2.08Mhz

[fpga/rpi-motor-control.git] / pmsm-control / divider.vhdl

diff --git a/pmsm-control/div8.vhdl b/pmsm-control/divider.vhdl
similarity index 58%
rename from pmsm-control/div8.vhdl
rename to pmsm-control/divider.vhdl
index f243183090361dc9c5c9580c55e4d401a37a7388..5f9a13fc49e197b95615da8d174b7b6482b3a658 100644 (file)
--- a/pmsm-control/div8.vhdl
+++ b/pmsm-control/divider.vhdl
@@ -1,33 +1,36 @@
-
+-- provides frequency division by 12
+-- initialy intended to make 4.17Mhz from 50Mhz 

 
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use work.util.all;
 
 
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use work.util.all;
 

-entity div8 is
+entity divider is

 
 port (
        clk_in: in std_logic;
 
 port (
        clk_in: in std_logic;

-       clk_out: out std_logic
+       div12: out std_logic

 );
 );

-end div8;
+end divider;

 
 
 
 

-architecture behavioral of div8 is
+architecture behavioral of divider is

        signal count : std_logic_vector (2 downto 0);
        signal count : std_logic_vector (2 downto 0);

+       signal tmp : std_logic;

 begin
        
        
        divider : process 
        begin
                wait until (clk_in'event and clk_in='1');
 begin
        
        
        divider : process 
        begin
                wait until (clk_in'event and clk_in='1');

-               if (count="111") then
+               if (count(2 downto 1)="11") then

                        count<="000";
                        count<="000";

+                       tmp <= not tmp;

                else
                        count <= std_logic_vector(unsigned(count) + 1);
                end if;
                else
                        count <= std_logic_vector(unsigned(count) + 1);
                end if;

-                       clk_out <= count(2);
+                       div12<=tmp;

     end process divider;
 
        
     end process divider;