Modified ADC clk frequency from 3.2 MHz to 2.08Mhz

[fpga/rpi-motor-control.git] / pmsm-control / rpi_pmsm_control.vhdl

diff --git a/pmsm-control/rpi_pmsm_control.vhdl b/pmsm-control/rpi_pmsm_control.vhdl
index 45ea914ac46af22bba59f04304c3b76918f55d25..4db7abf7b1104c896771e7194ef7473bbf47346c 100644 (file)
--- a/pmsm-control/rpi_pmsm_control.vhdl
+++ b/pmsm-control/rpi_pmsm_control.vhdl
@@ -133,11 +133,11 @@ architecture behavioral of rpi_mc_simple_dc is
        );
        end component;
        
-       component div8 is
+       --frequency division by 12
+       component divider is
        port (
-               --reset: in std_logic;
                clk_in: in std_logic;
-               clk_out: out std_logic
+               div12: out std_logic
        );
        end component;
        
@@ -183,7 +183,7 @@ architecture behavioral of rpi_mc_simple_dc is
        
        signal income_data_valid: std_logic;
        
-       signal clk_3M1: std_logic;
+       signal clk_4M17: std_logic;
        
        
        
@@ -242,16 +242,20 @@ begin
        end generate;
        
        
-       div8_map: div8 
+       div12_map: divider
        port map(
                --reset => income_data_valid,
                clk_in => gpio_clk,
-               clk_out => clk_3M1
+               div12 => clk_4M17
        );
        
+       -- ADC needs 3.2 MHz clk when powered from +5V Vcc
+       --           2.0 MHz clk when +2.7V Vcc
+       -- on the input is 4.17Mhz,but this frequency is divided inside adc_reader by 2 to 2.08 Mhz,
+       --        while we use +3.3V Vcc     
        adc_reader_map: adc_reader 
        port map(
-               clk =>clk_3M1,
+               clk =>clk_4M17,
                adc_reset => adc_reset,
                adc_miso => adc_miso,
                adc_channels => adc_channels,