-- SPI connected multichannel current ADC read and averaging
--
-- (c) 2015 Martin Prudek <prudemar@fel.cvut.cz>
-- SPI connected multichannel current ADC read and averaging
--
-- (c) 2015 Martin Prudek <prudemar@fel.cvut.cz>
- clk: in std_logic; --input clk
- adc_reset: in std_logic;
+ clk: in std_logic; --synchronous master clk
+ divided_clk : in std_logic; --divided clk - value suitable to sourcing voltage
+ adc_reset: in std_logic; --synchronous reset on rising edge
+
adc_sclk: out std_logic; --spi clk
adc_scs: out std_logic; --spi slave select
adc_mosi: out std_logic; --spi master out slave in
adc_sclk: out std_logic; --spi clk
adc_scs: out std_logic; --spi slave select
adc_mosi: out std_logic; --spi master out slave in
type channel_type is (ch0, ch1, ch2);
signal adc_data: std_logic_vector(11 downto 0);
type channel_type is (ch0, ch1, ch2);
signal adc_data: std_logic_vector(11 downto 0);
signal adc_address: std_logic_vector(2 downto 0);
signal cumul_data: std_logic_vector(71 downto 0); --unconsistent data, containing different amounts of measurments
signal prepared_data: std_logic_vector(71 downto 0); --consistent data, waiting for clk sync to propagate to output
signal adc_address: std_logic_vector(2 downto 0);
signal cumul_data: std_logic_vector(71 downto 0); --unconsistent data, containing different amounts of measurments
signal prepared_data: std_logic_vector(71 downto 0); --consistent data, waiting for clk sync to propagate to output
- adc_rst_old(0)<=adc_reset;
- adc_rst_old(1)<=adc_rst_old(0);
-
- if (adc_rst_old="01") then
+ adc_rst_prev<=adc_reset;
+ if (adc_rst_prev='0') and (adc_reset='1') then