1 -- provides frequency division by 12
2 -- initialy intended to make 4.17Mhz from 50Mhz
5 use ieee.std_logic_1164.all;
6 use ieee.numeric_std.all;
18 architecture behavioral of divider is
19 signal count : std_logic_vector (2 downto 0);
20 signal tmp : std_logic;
26 wait until (clk_in'event and clk_in='1');
27 if (count(2 downto 1)="11") then
31 count <= std_logic_vector(unsigned(count) + 1);