pmsm-control/div128.vhdl

   1 -- provides frequency division by 12
   2 -- initialy intended to make 4.17Mhz from 50Mhz
   3
   4 library ieee;
   5 use ieee.std_logic_1164.all;
   6 use ieee.numeric_std.all;
   7 use work.util.all;
   8
   9 entity div128 is
  10
  11 port (
  12         clk_in: in std_logic;
  13         rst: in std_logic;
  14         fail_safe: out std_logic
  15 );
  16 end div128;
  17
  18
  19 architecture behavioral of div128 is
  20         signal count : std_logic_vector (6 downto 0);
  21         signal rst_prev: std_logic;
  22 begin
  23
  24
  25         seq : process
  26         begin
  27                 wait until (clk_in'event and clk_in='1');
  28                 rst_prev <= rst;
  29                 if rst='1' and rst_prev='0' then
  30                         count <= "0000000";
  31                         fail_safe <= '0';
  32                 else
  33                         count <= std_logic_vector(unsigned(count) + 1);
  34                 end if;
  35
  36                 if count = "1111111" then
  37                         fail_safe <= '1';
  38                 else
  39                         fail_safe <= '0';
  40                 end if;
  41         end process;
  42
  43
  44
  45 end behavioral;
  46