pmsm-control/cnt_div.vhdl

   1 --
   2 -- * Counter - divider *
   3 --
   4 -- part of LXPWR motion control board (c) PiKRON Ltd
   5 -- idea by Pavel Pisa PiKRON Ltd <ppisa@pikron.com>
   6 --
   7 -- license: BSD
   8 --
   9 -- This file is used in "RPI PMS motor control" as frequency divider - divides by 6
  10
  11 library ieee;
  12 use ieee.std_logic_1164.all;
  13 use ieee.numeric_std.all;
  14
  15 entity cnt_div is
  16         generic (
  17                 cnt_width_g : natural := 4
  18         );
  19         port
  20         (
  21                 clk_i     : in std_logic;                               --clk to divide
  22                 en_i      : in std_logic;                               --enable bit?
  23                 reset_i   : in std_logic;                               --asynch. reset
  24                 ratio_i   : in std_logic_vector(cnt_width_g-1 downto 0);--initial value
  25                 q_out_o   : out std_logic                               --generates puls when counter underflows
  26         );
  27 end cnt_div;
  28
  29 architecture behavioral of cnt_div is
  30         signal cnt_val_s : natural range 0 to (2**cnt_width_g - 1);     --counter value before DFF
  31         signal cnt_val_r : natural range 0 to (2**cnt_width_g - 1);     --counter value after DFF
  32 begin
  33
  34 comb: process (reset_i, en_i, ratio_i, cnt_val_r)
  35         begin
  36                 if reset_i = '1' then --reset detection
  37                         cnt_val_s <= to_integer(unsigned(ratio_i));     --set initial value
  38                         q_out_o   <= '0';                               --reset output
  39                 else
  40                         if en_i = '0' then                              --stop-state
  41                                 cnt_val_s <= cnt_val_r;                 --hold the value
  42                                 q_out_o   <= '0';                       --reset output
  43                         else
  44                                 if cnt_val_r <= 1 then                  --counter underflows
  45                                         cnt_val_s <= to_integer(unsigned(ratio_i)); --set initial value
  46                                         q_out_o   <= '1';               --set output
  47                                 else
  48                                         cnt_val_s <= cnt_val_r - 1;     --decrement counter
  49                                         q_out_o   <= '0';               --reset output
  50                                 end if;
  51                         end if;
  52                 end if;
  53         end process;
  54
  55 seq: process
  56         begin
  57                 wait until clk_i'event and clk_i = '1';
  58                 cnt_val_r <= cnt_val_s;
  59         end process;
  60
  61 end behavioral;
  62