]> rtime.felk.cvut.cz Git - fpga/quadcount.git/commitdiff
Removed quadcount_tb as it do nothing
authorVladimir Burian <buriavl2@fel.cvut.cz>
Thu, 14 Apr 2011 11:38:25 +0000 (13:38 +0200)
committerVladimir Burian <buriavl2@fel.cvut.cz>
Thu, 14 Apr 2011 11:38:25 +0000 (13:38 +0200)
quadcount_tb.vhdl [deleted file]

diff --git a/quadcount_tb.vhdl b/quadcount_tb.vhdl
deleted file mode 100644 (file)
index a15c6ba..0000000
+++ /dev/null
@@ -1,43 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
-entity quadcount_tb is
-end quadcount_tb;
-
-architecture behavioral of quadcount_tb is
-  component qcounter
-    port (
-      clock: in std_logic;
-      reset: in std_logic;
-      a, b: in std_logic;
-      qcount: out std_logic_vector (31 downto 0);
-      a_rise, a_fall, b_rise, b_fall, ab_event: out std_logic;
-      ab_error: out std_logic
-    );
-  end component;
-
-  signal clock, reset, a, b: std_logic;
-begin
-  qc0: qcounter
-    port map (
-      clock => clock,
-      reset => reset,
-      a => a,
-      b => b
-    );
-
-  reset <= '0';
-  a <= '0';
-  b <= '0';
-  
-  test: process
-  begin
-    clock <= '0';
-    wait for 1 us;
-    clock <= '1';
-    wait for 1 us;
-  end process;
-end behavioral;