Resets changed from asynchronous to synchronous.

diff --git a/counter.vhd b/counter.vhd
index 3161c631b08b98a7f571b98698e2005d2aadd621..0994e811f7da1bfd78fe0e81e2f0b81f02560b31 100644 (file)
--- a/counter.vhd
+++ b/counter.vhd
@@ -42,15 +42,17 @@ begin
   
   COUTER : process (clk, reset) is
   begin
-    if reset = '1' then
-      cnt <= (others => '0');
-
-    elsif rising_edge(clk) then
-      if clk_en = '1' then
-        if eq_max = '1' then
-          cnt <= (others => '0');
-        else
-          cnt <= cnt + 1;
+    if rising_edge(clk) then
+      if reset = '1' then
+        cnt <= (others => '0');
+        
+      else
+        if clk_en = '1' then
+          if eq_max = '1' then
+            cnt <= (others => '0');
+          else
+            cnt <= cnt + 1;
+          end if;
         end if;
       end if;
     end if;

diff --git a/irc_dump.vhd b/irc_dump.vhd
index ee8b1b20465c17bcd03cd0b951c2baf1e8744043..c48ce4ed0d8447337b9b97c34a8661dabc6b163d 100644 (file)
--- a/irc_dump.vhd
+++ b/irc_dump.vhd
@@ -50,11 +50,12 @@ begin
 
   process (CLK_I, RST_I) is
   begin
-    if RST_I = '1' then
-      INNER_ACK <= '0';
-      
-    elsif rising_edge(CLK_I) then
-      INNER_ACK <= STB_I;
+    if rising_edge(CLK_I) then
+      if RST_I = '1' then
+        INNER_ACK <= '0';
+      else
+        INNER_ACK <= STB_I;
+      end if;
     end if;
   end process;
   

diff --git a/mcc_master.vhd b/mcc_master.vhd
index 0a09de8cad12a8c31323692b4b00388bc5920147..fca6652697d325b15ab7d4782484f995c584afa3 100644 (file)
--- a/mcc_master.vhd
+++ b/mcc_master.vhd
@@ -67,27 +67,29 @@ begin
 
   MCC_EXEC_LOGIC : process (RST_I, CLK_I) is
   begin
-    if RST_I = '1' then
-      mcc_ack_inner <= (others => '0');
-      mcc_stb_inner <= (others => '0');
-
-    elsif rising_edge(CLK_I) then
-      if mcc_exec = '0' then
+    if rising_edge(CLK_I) then
+      if RST_I = '1' then
         mcc_ack_inner <= (others => '0');
         mcc_stb_inner <= (others => '0');
-        
+
       else
-        mcc_ack_inner (0) <= mcc_exec;
-        
-        for i in 0 to MCC_W-1 loop
-          if mcc_mask (i) = '1' then
-            mcc_ack_inner (i+1) <= MCC_ACK_I (i);
-            mcc_stb_inner (i)   <= mcc_ack_inner (i);
-          else
-            mcc_ack_inner (i+1) <= mcc_ack_inner (i);
-            mcc_stb_inner (i)   <= '0';
-          end if;
-        end loop;
+        if mcc_exec = '0' then
+          mcc_ack_inner <= (others => '0');
+          mcc_stb_inner <= (others => '0');
+          
+        else
+          mcc_ack_inner (0) <= mcc_exec;
+          
+          for i in 0 to MCC_W-1 loop
+            if mcc_mask (i) = '1' then
+              mcc_ack_inner (i+1) <= MCC_ACK_I (i);
+              mcc_stb_inner (i)   <= mcc_ack_inner (i);
+            else
+              mcc_ack_inner (i+1) <= mcc_ack_inner (i);
+              mcc_stb_inner (i)   <= '0';
+            end if;
+          end loop;
+        end if;
       end if;
     end if;
   end process;

diff --git a/pwm.vhd b/pwm.vhd
index 3590d5423041628c317a966c69c3bf6069edae3d..4ac8765f48e1ece55a00f0b2bb3c7d2262d29b9d 100644 (file)
--- a/pwm.vhd
+++ b/pwm.vhd
@@ -53,12 +53,13 @@ begin
   -- Peripheral register
   PWM_REGISTER : process (clk, reset)
   begin
-    if reset = '1' then
-      reg <= (others => '0');
-
-    elsif rising_edge(clk) then
-      if we = '1' then
-        reg <= din;
+    if rising_edge(clk) then
+      if reset = '1' then
+        reg <= (others => '0');
+      else
+        if we = '1' then
+          reg <= din;
+        end if;
       end if;
     end if;
   end process;
@@ -69,18 +70,20 @@ begin
   -- with next clk edge. Pwm output is delayed by one clock.
   PWM_GEN : process (clk, reset)
   begin
-    if reset = '1' then
-      pwm <= '0';
-      
-    elsif rising_edge(clk) then
-      if pwm_cyc = '1' then
-        cmp <= reg;
-      end if;
-      
-      if pwm_cnt < cmp then
-        pwm <= '1';
-      else
+    if rising_edge(clk) then
+      if reset = '1' then
         pwm <= '0';
+
+      else  
+        if pwm_cyc = '1' then
+          cmp <= reg;
+        end if;
+        
+        if pwm_cnt < cmp then
+          pwm <= '1';
+        else
+          pwm <= '0';
+        end if;
       end if;
     end if;
   end process;

diff --git a/pwm_dump.vhd b/pwm_dump.vhd
index 8d942a1faa48618f8a7d32644950200a7455282f..adcf7326c1c14e38a97436555cc0713f2e59565c 100644 (file)
--- a/pwm_dump.vhd
+++ b/pwm_dump.vhd
@@ -54,27 +54,29 @@ begin
   
   FSM : process (CLK_I, RST_I) is
   begin
-    if RST_I = '1' then
-      state     <= ready;
-      INNER_ACK <= '0';
-      PWM_STB_O <= '0';
+    if rising_edge(CLK_I) then
+      if RST_I = '1' then
+        state     <= ready;
+        INNER_ACK <= '0';
+        PWM_STB_O <= '0';
       
-    elsif rising_edge(CLK_I) then
-      case state is
-        when ready =>
-          if STB_I = '1' then
-            state     <= done;
-            INNER_ACK <= '1';
-            PWM_STB_O <= '1';
-          end if;
+      else  
+        case state is
+          when ready =>
+            if STB_I = '1' then
+              state     <= done;
+              INNER_ACK <= '1';
+              PWM_STB_O <= '1';
+            end if;
 
-        when done =>
-          PWM_STB_O <= '0';
-          if STB_I = '0' then
-            state     <= ready;
-            INNER_ACK <= '0';
-          end if;
-      end case;
+          when done =>
+            PWM_STB_O <= '0';
+            if STB_I = '0' then
+              state     <= ready;
+              INNER_ACK <= '0';
+            end if;
+        end case;
+      end if;
     end if;
   end process;
   

diff --git a/sequencer.vhd b/sequencer.vhd
index 59013e48051e20e1b9e984c8a1bca3064a10521d..d1a0ce9c321d74fecce593311b0cbf7da36c5665 100644 (file)
--- a/sequencer.vhd
+++ b/sequencer.vhd
@@ -60,46 +60,48 @@ begin
 
   FSM : process (CLK_I, RST_I) is
   begin
-    if RST_I = '1' then
-      state     <= ready;
-      INNER_ACK <= '0';
-      SL_STB_O  <= '0';
-
-    elsif rising_edge(CLK_I) then
-      case state is
-        when ready =>
-          if STB_I = '1' then
-            state    <= phase1;
+    if rising_edge(CLK_I) then
+      if RST_I = '1' then
+        state     <= ready;
+        INNER_ACK <= '0';
+        SL_STB_O  <= '0';
+
+      else
+        case state is
+          when ready =>
+            if STB_I = '1' then
+              state    <= phase1;
+              SL_STB_O <= '1';
+            end if;
+
+          when phase1 =>
+            if SL_ACK_I = '1' then
+              state    <= phase2;
+              SL_STB_O <= '0';
+            end if;
+            
+          when phase2 =>
             SL_STB_O <= '1';
-          end if;
-
-        when phase1 =>
-          if SL_ACK_I = '1' then
-            state    <= phase2;
-            SL_STB_O <= '0';
-          end if;
-          
-        when phase2 =>
-          SL_STB_O <= '1';
-          if SL_ACK_I = '1' then
-            state    <= phase3;
-            SL_STB_O <= '0';
-          end if;
-
-        when phase3 =>
-          SL_STB_O <= '1';
-          if SL_ACK_I = '1' then
-            state     <= done;
-            INNER_ACK <= '1';
-            SL_STB_O  <= '0';
-          end if;
-
-        when done =>
-          if STB_I = '0' then
-            state     <= ready;
-            INNER_ACK <= '0';
-          end if;
-      end case;
+            if SL_ACK_I = '1' then
+              state    <= phase3;
+              SL_STB_O <= '0';
+            end if;
+
+          when phase3 =>
+            SL_STB_O <= '1';
+            if SL_ACK_I = '1' then
+              state     <= done;
+              INNER_ACK <= '1';
+              SL_STB_O  <= '0';
+            end if;
+
+          when done =>
+            if STB_I = '0' then
+              state     <= ready;
+              INNER_ACK <= '0';
+            end if;
+        end case;
+      end if;
     end if;
   end process;
 

diff --git a/vector_scale.vhd b/vector_scale.vhd
index d1c6306c34e731cf115cf379aeae805f03931e3e..40492cb096f33783686af5d54f234c3d5d5dcfd2 100644 (file)
--- a/vector_scale.vhd
+++ b/vector_scale.vhd
@@ -78,44 +78,46 @@ begin
   
   FSM : process (CLK_I, RST_I) is
   begin
-    if RST_I = '1' then
-      state     <= ready;
-      INNER_ACK <= '0';
-      IRF_STB_O <= '0';
-      IRF_WE_O  <= '0';
-      
-    elsif rising_edge(CLK_I) then
-      case state is
-        when ready =>
-          if STB_I = '1' then
-            state     <= load_scale;
-            IRF_ADR_O <= SCALE_ADR;
-            IRF_STB_O <= '1';
-          end if;
-
-        when load_scale =>
-          state     <= load_vector;
-          IRF_ADR_O <= VECTOR_ADR;
-
-        when load_vector =>
-          state     <= save_scaled;
-          IRF_ADR_O <= SCALED_ADR;
-          MUL_A     <= IRF_DAT_I;
-          
-        when save_scaled =>
-          state     <= done;
-          INNER_ACK <= '1';
-          IRF_WE_O  <= '1';
-          MUL_B     <= conv_std_logic_vector(signed(biased_to_twos(IRF_DAT_I(VECTOR_W-1 downto 0))), 16);
-          
-        when done =>
-          IRF_STB_O <= '0';
-          IRF_WE_O  <= '0';
-          if STB_I = '0' then
-            state     <= ready;
-            INNER_ACK <= '0';
-          end if;
-      end case;
+    if rising_edge(CLK_I) then
+      if RST_I = '1' then
+        state     <= ready;
+        INNER_ACK <= '0';
+        IRF_STB_O <= '0';
+        IRF_WE_O  <= '0';
+
+      else
+        case state is
+          when ready =>
+            if STB_I = '1' then
+              state     <= load_scale;
+              IRF_ADR_O <= SCALE_ADR;
+              IRF_STB_O <= '1';
+            end if;
+
+          when load_scale =>
+            state     <= load_vector;
+            IRF_ADR_O <= VECTOR_ADR;
+
+          when load_vector =>
+            state     <= save_scaled;
+            IRF_ADR_O <= SCALED_ADR;
+            MUL_A     <= IRF_DAT_I;
+            
+          when save_scaled =>
+            state     <= done;
+            INNER_ACK <= '1';
+            IRF_WE_O  <= '1';
+            MUL_B     <= conv_std_logic_vector(signed(biased_to_twos(IRF_DAT_I(VECTOR_W-1 downto 0))), 16);
+            
+          when done =>
+            IRF_STB_O <= '0';
+            IRF_WE_O  <= '0';
+            if STB_I = '0' then
+              state     <= ready;
+              INNER_ACK <= '0';
+            end if;
+        end case;
+      end if;
     end if;
   end process;