Resets changed from asynchronous to synchronous.

[fpga/pwm.git] / irc_dump.vhd

diff --git a/irc_dump.vhd b/irc_dump.vhd
index ee8b1b20465c17bcd03cd0b951c2baf1e8744043..c48ce4ed0d8447337b9b97c34a8661dabc6b163d 100644 (file)
--- a/irc_dump.vhd
+++ b/irc_dump.vhd
@@ -50,11 +50,12 @@ begin
 
   process (CLK_I, RST_I) is
   begin
-    if RST_I = '1' then
-      INNER_ACK <= '0';
-      
-    elsif rising_edge(CLK_I) then
-      INNER_ACK <= STB_I;
+    if rising_edge(CLK_I) then
+      if RST_I = '1' then
+        INNER_ACK <= '0';
+      else
+        INNER_ACK <= STB_I;
+      end if;
     end if;
   end process;