Resets changed from asynchronous to synchronous.

[fpga/pwm.git] / counter.vhd

diff --git a/counter.vhd b/counter.vhd
index 3161c631b08b98a7f571b98698e2005d2aadd621..0994e811f7da1bfd78fe0e81e2f0b81f02560b31 100644 (file)
--- a/counter.vhd
+++ b/counter.vhd
@@ -42,15 +42,17 @@ begin
   
   COUTER : process (clk, reset) is
   begin
-    if reset = '1' then
-      cnt <= (others => '0');
-
-    elsif rising_edge(clk) then
-      if clk_en = '1' then
-        if eq_max = '1' then
-          cnt <= (others => '0');
-        else
-          cnt <= cnt + 1;
+    if rising_edge(clk) then
+      if reset = '1' then
+        cnt <= (others => '0');
+        
+      else
+        if clk_en = '1' then
+          if eq_max = '1' then
+            cnt <= (others => '0');
+          else
+            cnt <= cnt + 1;
+          end if;
         end if;
       end if;
     end if;