2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
4 use ieee.std_logic_unsigned.all;
6 --------------------------------------------------------------------------------
10 IRF_ADR_W : integer := 5;
12 PWMMIN_OFF : integer := 6;
13 P_BASE : integer := 16;
14 PWM_OFF : integer := 1;
15 PWM_W : integer := 10);
17 -- Primary slave intefrace
18 ACK_O : out std_logic;
23 PWM_DAT_O : out std_logic_vector (PWM_W-1 downto 0);
24 PWM_STB_O : out std_logic := '0';
25 -- Shared dual-port memory
26 IRF_ACK_I : in std_logic;
27 IRF_ADR_O : out std_logic_vector (IRF_ADR_W-1 downto 0);
28 IRF_DAT_I : in std_logic_vector (15 downto 0);
29 IRF_STB_O : out std_logic);
30 end entity pwm_min_dump;
32 --------------------------------------------------------------------------------
34 architecture behavioral of pwm_min_dump is
36 type state_t is (ready, dump, done);
37 subtype irf_adr_t is std_logic_vector (IRF_ADR_W-1 downto 0);
39 constant PWMMIN_ADR : irf_adr_t := conv_std_logic_vector(BASE+PWMMIN_OFF, IRF_ADR_W);
40 constant PWM_ADR : irf_adr_t := conv_std_logic_vector(P_BASE + PWM_OFF, IRF_ADR_W);
42 signal state : state_t := ready;
44 signal ack : std_logic := '0';
45 --signal pwm_min : std_logic_vector (PWM_DAT_O'RANGE);
46 signal pwm_min : std_logic_vector (PWM_DAT_O'range);
47 signal pwm_stb : std_logic := '0';
48 signal irf_adr : irf_adr_t := PWMMIN_ADR;
49 signal irf_we : std_logic := '0';
51 --------------------------------------------------------------------------------
55 ACK_O <= STB_I and ack;
57 PWM_DAT_O <= IRF_DAT_I(pwm_min'RANGE) - pwm_min;
64 FSM : process (CLK_I, RST_I) is
69 irf_adr <= PWMMIN_ADR;
72 elsif rising_edge(CLK_I) then
84 pwm_min <= IRF_DAT_I(pwm_min'RANGE);
91 irf_adr <= PWMMIN_ADR;
97 end architecture behavioral;