2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
4 use ieee.std_logic_unsigned.all;
9 --------------------------------------------------------------------------------
15 IRF_ADR_W : integer := 5);
17 -- Primary slave intefrace
18 ACK_O : out std_logic := '0';
22 -- Motion Control Chain
23 MCC_STB_O : out std_logic_vector (MCC_W-1 downto 0) := (others => '0');
24 MCC_ACK_I : in std_logic_vector (MCC_W-1 downto 0);
25 MCC_MUX_CODE : out std_logic_vector (MUX_W-1 downto 0) := (others => '0');
26 MCC_MUX_EN : out std_logic := '0';
27 -- Shared dual-port memory
28 IRF_ACK_I : in std_logic;
29 IRF_ADR_O : out std_logic_vector (IRF_ADR_W-1 downto 0);
30 IRF_DAT_I : in std_logic_vector (15 downto 0);
31 IRF_DAT_O : out std_logic_vector (15 downto 0);
32 IRF_STB_O : out std_logic := '0';
33 IRF_WE_O : out std_logic);
34 end entity mcc_master;
36 --------------------------------------------------------------------------------
38 architecture behavioral of mcc_master is
40 type state_t is (ready, read_mask, do_mcc, done);
42 signal state : state_t := ready;
44 signal mcc_mask : std_logic_vector (MCC_W-1 downto 0);
45 signal mcc_ack_inner : std_logic_vector (MCC_W downto 0) := (others => '0');
46 signal mcc_stb_inner : std_logic_vector (MCC_W-1 downto 0) := (others => '0');
47 signal mux_code_inner : std_logic_vector (MUX_W-1 downto 0);
48 signal mcc_exec : std_logic := '0';
50 --------------------------------------------------------------------------------
54 IRF_ADR_O <= conv_std_logic_vector(0, IRF_ADR_W);
55 IRF_DAT_O <= (others => '-');
59 priority_encoder_1: entity work.priority_encoder
65 code => mux_code_inner);
68 MCC_EXEC_LOGIC : process (RST_I, CLK_I) is
70 if rising_edge(CLK_I) then
72 mcc_ack_inner <= (others => '0');
73 mcc_stb_inner <= (others => '0');
76 if mcc_exec = '0' then
77 mcc_ack_inner <= (others => '0');
78 mcc_stb_inner <= (others => '0');
81 mcc_ack_inner (0) <= mcc_exec;
83 for i in 0 to MCC_W-1 loop
84 if mcc_mask (i) = '1' then
85 mcc_ack_inner (i+1) <= MCC_ACK_I (i);
86 mcc_stb_inner (i) <= mcc_ack_inner (i);
88 mcc_ack_inner (i+1) <= mcc_ack_inner (i);
89 mcc_stb_inner (i) <= '0';
98 LATCHES : process (RST_I, CLK_I) is
101 MCC_STB_O <= (others => '0');
102 MCC_MUX_CODE <= (others => '0');
104 elsif rising_edge(CLK_I) then
105 MCC_STB_O <= mcc_stb_inner;
106 MCC_MUX_CODE <= mux_code_inner;
111 FSM : process (CLK_I, RST_I) is
120 elsif rising_edge(CLK_I) then
129 if IRF_ACK_I = '1' then
131 mcc_mask <= IRF_DAT_I (mcc_mask'RANGE);
137 if mcc_ack_inner (MCC_W) = '1' then
154 end architecture behavioral;