2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
4 use ieee.std_logic_unsigned.all;
6 --------------------------------------------------------------------------------
10 IRF_ADR_W : integer := 5;
12 IRC_OFF : integer := 1;
13 ABASE_OFF : integer := 2;
14 APER_OFF : integer := 3;
15 A_OFF : integer := 4);
17 -- Primary slave interface
18 ACK_O : out std_logic := '0';
22 -- Master interface to the interface memory
23 IRF_ACK_I : in std_logic;
24 IRF_ADR_O : out std_logic_vector (IRF_ADR_W-1 downto 0);
25 IRF_DAT_I : in std_logic_vector (15 downto 0);
26 IRF_DAT_O : out std_logic_vector (15 downto 0);
27 IRF_STB_O : out std_logic := '0';
28 IRF_WE_O : out std_logic := '0';
30 BAD_BASE : out std_logic);
33 --------------------------------------------------------------------------------
35 architecture behavioral of irc_base is
37 type state_t is (ready, nop, load_irc, load_base, load_per, do_correction, save, done);
38 subtype irf_adr_t is std_logic_vector (IRF_ADR_W-1 downto 0);
40 constant IRC_ADR : irf_adr_t := conv_std_logic_vector(BASE+IRC_OFF, IRF_ADR_W);
41 constant BASE_ADR : irf_adr_t := conv_std_logic_vector(BASE+ABASE_OFF, IRF_ADR_W);
42 constant PER_ADR : irf_adr_t := conv_std_logic_vector(BASE+APER_OFF, IRF_ADR_W);
43 constant ANG_ADR : irf_adr_t := conv_std_logic_vector(BASE+A_OFF, IRF_ADR_W);
46 signal state : state_t := ready;
47 signal irc : std_logic_vector (15 downto 0);
48 signal irc_base : std_logic_vector (15 downto 0);
49 signal irc_per : std_logic_vector (15 downto 0);
51 signal angle : std_logic_vector (15 downto 0);
52 signal new_base : std_logic_vector (15 downto 0);
53 signal lower : std_logic;
54 signal higher : std_logic;
56 --------------------------------------------------------------------------------
60 BAD_BASE <= '1' when state = save and (lower = '1' or higher = '1') else '0';
62 lower <= angle (angle'HIGH);
63 higher <= '1' when angle >= irc_per and lower = '0' else '0';
65 angle <= irc - irc_base;
67 new_base <= irc_base - irc_per when lower = '1' else
68 irc_base + irc_per when higher = '1' else
72 FSM : process (CLK_I) is
74 if rising_edge(CLK_I) then
75 if RST_I = '1' or STB_I = '0' then
92 IRF_ADR_O <= BASE_ADR;
101 irc_base <= IRF_DAT_I;
104 state <= do_correction;
105 irc_per <= IRF_DAT_I;
108 when do_correction =>
110 irc_base <= new_base;
111 IRF_ADR_O <= BASE_ADR;
112 IRF_DAT_O <= new_base;
118 IRF_ADR_O <= ANG_ADR;
135 end architecture behavioral;