1 //----------------------------------------------------------------------------
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28 //----------------------------------------------------------------------------
30 // *File Name: template_periph_16b.v
32 // *Module Description:
33 // 16 bit peripheral template.
36 // - Olivier Girard, olgirard@gmail.com
38 //----------------------------------------------------------------------------
40 // $LastChangedBy: olivier.girard $
41 // $LastChangedDate: 2010-03-07 09:09:38 +0100 (Sun, 07 Mar 2010) $
42 //----------------------------------------------------------------------------
43 `include "timescale.v"
44 `include "openMSP430_defines.v"
46 module template_periph_16b (
49 per_dout, // Peripheral data output
52 mclk, // Main system clock
53 per_addr, // Peripheral address
54 per_din, // Peripheral data input
55 per_en, // Peripheral enable (high active)
56 per_wen, // Peripheral write enable (high active)
57 puc // Main system reset
62 output [15:0] per_dout; // Peripheral data output
66 input mclk; // Main system clock
67 input [7:0] per_addr; // Peripheral address
68 input [15:0] per_din; // Peripheral data input
69 input per_en; // Peripheral enable (high active)
70 input [1:0] per_wen; // Peripheral write enable (high active)
71 input puc; // Main system reset
74 //=============================================================================
75 // 1) PARAMETER DECLARATION
76 //=============================================================================
79 parameter CNTRL1 = 9'h190;
80 parameter CNTRL2 = 9'h192;
81 parameter CNTRL3 = 9'h194;
82 parameter CNTRL4 = 9'h196;
85 // Register one-hot decoder
86 parameter CNTRL1_D = (512'h1 << CNTRL1);
87 parameter CNTRL2_D = (512'h1 << CNTRL2);
88 parameter CNTRL3_D = (512'h1 << CNTRL3);
89 parameter CNTRL4_D = (512'h1 << CNTRL4);
92 //============================================================================
93 // 2) REGISTER DECODER
94 //============================================================================
96 // Register address decode
99 case ({per_addr,1'b0})
100 CNTRL1 : reg_dec = CNTRL1_D;
101 CNTRL2 : reg_dec = CNTRL2_D;
102 CNTRL3 : reg_dec = CNTRL3_D;
103 CNTRL4 : reg_dec = CNTRL4_D;
104 default: reg_dec = {512{1'b0}};
108 wire reg_write = |per_wen & per_en;
109 wire reg_read = ~|per_wen & per_en;
111 // Read/Write vectors
112 wire [511:0] reg_wr = reg_dec & {512{reg_write}};
113 wire [511:0] reg_rd = reg_dec & {512{reg_read}};
116 //============================================================================
118 //============================================================================
124 wire cntrl1_wr = reg_wr[CNTRL1];
126 always @ (posedge mclk or posedge puc)
127 if (puc) cntrl1 <= 16'h0000;
128 else if (cntrl1_wr) cntrl1 <= per_din;
135 wire cntrl2_wr = reg_wr[CNTRL2];
137 always @ (posedge mclk or posedge puc)
138 if (puc) cntrl2 <= 16'h0000;
139 else if (cntrl2_wr) cntrl2 <= per_din;
146 wire cntrl3_wr = reg_wr[CNTRL3];
148 always @ (posedge mclk or posedge puc)
149 if (puc) cntrl3 <= 16'h0000;
150 else if (cntrl3_wr) cntrl3 <= per_din;
157 wire cntrl4_wr = reg_wr[CNTRL4];
159 always @ (posedge mclk or posedge puc)
160 if (puc) cntrl4 <= 16'h0000;
161 else if (cntrl4_wr) cntrl4 <= per_din;
164 //============================================================================
165 // 4) DATA OUTPUT GENERATION
166 //============================================================================
169 wire [15:0] cntrl1_rd = cntrl1 & {16{reg_rd[CNTRL1]}};
170 wire [15:0] cntrl2_rd = cntrl2 & {16{reg_rd[CNTRL2]}};
171 wire [15:0] cntrl3_rd = cntrl3 & {16{reg_rd[CNTRL3]}};
172 wire [15:0] cntrl4_rd = cntrl4 & {16{reg_rd[CNTRL4]}};
174 wire [15:0] per_dout = cntrl1_rd |
180 endmodule // template_periph_16b
182 `include "openMSP430_undefines.v"