1 //----------------------------------------------------------------------------
2 // Copyright (C) 2001 Authors
4 // This source file may be used and distributed without restriction provided
5 // that this copyright statement is not removed from the file and that any
6 // derivative work contains the original copyright notice and the associated
9 // This source file is free software; you can redistribute it and/or modify
10 // it under the terms of the GNU Lesser General Public License as published
11 // by the Free Software Foundation; either version 2.1 of the License, or
12 // (at your option) any later version.
14 // This source is distributed in the hope that it will be useful, but WITHOUT
15 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
17 // License for more details.
19 // You should have received a copy of the GNU Lesser General Public License
20 // along with this source; if not, write to the Free Software Foundation,
21 // Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
23 //----------------------------------------------------------------------------
25 // *File Name: omsp_clock_module.v
27 // *Module Description:
28 // Basic clock module implementation.
29 // Since the openMSP430 mainly targets FPGA and hobby
30 // designers. The clock structure has been greatly
31 // symplified in order to ease integration.
32 // See online wiki for more info.
35 // - Olivier Girard, olgirard@gmail.com
37 //----------------------------------------------------------------------------
39 // $LastChangedBy: olivier.girard $
40 // $LastChangedDate: 2009-12-29 20:10:34 +0100 (Tue, 29 Dec 2009) $
41 //----------------------------------------------------------------------------
42 `include "timescale.v"
43 `include "openMSP430_defines.v"
45 module omsp_clock_module (
48 aclk_en, // ACLK enable
49 mclk, // Main system clock
50 per_dout, // Peripheral data output
51 por, // Power-on reset
52 puc, // Main system reset
53 smclk_en, // SMCLK enable
56 dbg_reset, // Reset CPU from debug interface
57 dco_clk, // Fast oscillator (fast clock)
58 lfxt_clk, // Low frequency oscillator (typ 32kHz)
59 oscoff, // Turns off LFXT1 clock input
60 per_addr, // Peripheral address
61 per_din, // Peripheral data input
62 per_en, // Peripheral enable (high active)
63 per_wen, // Peripheral write enable (high active)
64 reset_n, // Reset Pin (low active)
65 scg1, // System clock generator 1. Turns off the SMCLK
66 wdt_reset // Watchdog-timer reset
71 output aclk_en; // ACLK enable
72 output mclk; // Main system clock
73 output [15:0] per_dout; // Peripheral data output
74 output por; // Power-on reset
75 output puc; // Main system reset
76 output smclk_en; // SMCLK enable
80 input dbg_reset; // Reset CPU from debug interface
81 input dco_clk; // Fast oscillator (fast clock)
82 input lfxt_clk; // Low frequency oscillator (typ 32kHz)
83 input oscoff; // Turns off LFXT1 clock input
84 input [7:0] per_addr; // Peripheral address
85 input [15:0] per_din; // Peripheral data input
86 input per_en; // Peripheral enable (high active)
87 input [1:0] per_wen; // Peripheral write enable (high active)
88 input reset_n; // Reset Pin (low active)
89 input scg1; // System clock generator 1. Turns off the SMCLK
90 input wdt_reset; // Watchdog-timer reset
93 //=============================================================================
94 // 1) PARAMETER DECLARATION
95 //=============================================================================
98 parameter BCSCTL1 = 9'h057;
99 parameter BCSCTL2 = 9'h058;
101 // Register one-hot decoder
102 parameter BCSCTL1_D = (256'h1 << (BCSCTL1 /2));
103 parameter BCSCTL2_D = (256'h1 << (BCSCTL2 /2));
106 //============================================================================
107 // 2) REGISTER DECODER
108 //============================================================================
110 // Register address decode
114 (BCSCTL1 /2): reg_dec = BCSCTL1_D;
115 (BCSCTL2 /2): reg_dec = BCSCTL2_D;
116 default : reg_dec = {256{1'b0}};
120 wire reg_lo_write = per_wen[0] & per_en;
121 wire reg_hi_write = per_wen[1] & per_en;
122 wire reg_read = ~|per_wen & per_en;
124 // Read/Write vectors
125 wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
126 wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}};
127 wire [255:0] reg_rd = reg_dec & {256{reg_read}};
130 //============================================================================
132 //============================================================================
137 wire bcsctl1_wr = BCSCTL1[0] ? reg_hi_wr[BCSCTL1/2] : reg_lo_wr[BCSCTL1/2];
138 wire [7:0] bcsctl1_nxt = BCSCTL1[0] ? per_din[15:8] : per_din[7:0];
140 always @ (posedge mclk or posedge puc)
141 if (puc) bcsctl1 <= 8'h00;
142 else if (bcsctl1_wr) bcsctl1 <= bcsctl1_nxt & 8'h30; // Mask unused bits
148 wire bcsctl2_wr = BCSCTL2[0] ? reg_hi_wr[BCSCTL2/2] : reg_lo_wr[BCSCTL2/2];
149 wire [7:0] bcsctl2_nxt = BCSCTL2[0] ? per_din[15:8] : per_din[7:0];
151 always @ (posedge mclk or posedge puc)
152 if (puc) bcsctl2 <= 8'h00;
153 else if (bcsctl2_wr) bcsctl2 <= bcsctl2_nxt & 8'h0e; // Mask unused bits
156 //============================================================================
157 // 4) DATA OUTPUT GENERATION
158 //============================================================================
161 wire [15:0] bcsctl1_rd = (bcsctl1 & {8{reg_rd[BCSCTL1/2]}}) << (8 & {4{BCSCTL1[0]}});
162 wire [15:0] bcsctl2_rd = (bcsctl2 & {8{reg_rd[BCSCTL2/2]}}) << (8 & {4{BCSCTL2[0]}});
164 wire [15:0] per_dout = bcsctl1_rd |
168 //=============================================================================
169 // 5) CLOCK GENERATION
170 //=============================================================================
172 // Synchronize LFXT_CLK & edge detection
173 //---------------------------------------
174 reg [2:0] lfxt_clk_s;
176 always @ (posedge mclk or posedge puc)
177 if (puc) lfxt_clk_s <= 3'b000;
178 else lfxt_clk_s <= {lfxt_clk_s[1:0], lfxt_clk};
180 wire lfxt_clk_en = (lfxt_clk_s[1] & ~lfxt_clk_s[2]) & ~(oscoff & ~bcsctl2[`SELS]);
183 // Generate main system clock
184 //----------------------------
187 wire mclk_n = !dco_clk;
191 //----------------------------
195 wire aclk_en = lfxt_clk_en & ((bcsctl1[`DIVAx]==2'b00) ? 1'b1 :
196 (bcsctl1[`DIVAx]==2'b01) ? aclk_div[0] :
197 (bcsctl1[`DIVAx]==2'b10) ? &aclk_div[1:0] :
200 always @ (posedge mclk or posedge puc)
201 if (puc) aclk_div <= 3'h0;
202 else if ((bcsctl1[`DIVAx]!=2'b00) & lfxt_clk_en) aclk_div <= aclk_div+3'h1;
206 //----------------------------
210 wire smclk_in = ~scg1 & (bcsctl2[`SELS] ? lfxt_clk_en : 1'b1);
212 wire smclk_en = smclk_in & ((bcsctl2[`DIVSx]==2'b00) ? 1'b1 :
213 (bcsctl2[`DIVSx]==2'b01) ? smclk_div[0] :
214 (bcsctl2[`DIVSx]==2'b10) ? &smclk_div[1:0] :
217 always @ (posedge mclk or posedge puc)
218 if (puc) smclk_div <= 3'h0;
219 else if ((bcsctl2[`DIVSx]!=2'b00) & smclk_in) smclk_div <= smclk_div+3'h1;
222 //=============================================================================
223 // 6) RESET GENERATION
224 //=============================================================================
226 // Generate synchronized POR
227 wire por_reset = !reset_n;
230 always @(posedge mclk_n or posedge por_reset)
231 if (por_reset) por_s <= 2'b11;
232 else por_s <= {por_s[0], 1'b0};
235 // Generate main system reset
236 wire puc_reset = por_reset | wdt_reset | dbg_reset;
239 always @(posedge mclk_n or posedge puc_reset)
240 if (puc_reset) puc_s <= 2'b11;
241 else puc_s <= {puc_s[0], 1'b0};
245 endmodule // omsp_clock_module
247 `include "openMSP430_undefines.v"