]> rtime.felk.cvut.cz Git - fpga/openmsp430.git/blob - top/top_8_32_mul/openMSP430_8_32_mul.bmm
Added ready to use openMSP430 entity.
[fpga/openmsp430.git] / top / top_8_32_mul / openMSP430_8_32_mul.bmm
1 // ram_generic: 2x16kB, BRAM_TYPE=RAMB16_S2
2 ADDRESS_SPACE blockrom RAMB16 [0x8000:0xffff]
3   BUS_BLOCK
4       <path>/p_ram_lo/BLOCKS[0].RAMB16_S2.B[3].BRAM [7:6];
5       <path>/p_ram_lo/BLOCKS[0].RAMB16_S2.B[2].BRAM [5:4];
6       <path>/p_ram_lo/BLOCKS[0].RAMB16_S2.B[1].BRAM [3:2];
7       <path>/p_ram_lo/BLOCKS[0].RAMB16_S2.B[0].BRAM [1:0];
8       <path>/p_ram_hi/BLOCKS[0].RAMB16_S2.B[3].BRAM [15:14];
9       <path>/p_ram_hi/BLOCKS[0].RAMB16_S2.B[2].BRAM [13:12];
10       <path>/p_ram_hi/BLOCKS[0].RAMB16_S2.B[1].BRAM [11:10];
11       <path>/p_ram_hi/BLOCKS[0].RAMB16_S2.B[0].BRAM [9:8];
12   END_BUS_BLOCK;
13   BUS_BLOCK
14       <path>/p_ram_lo/BLOCKS[1].RAMB16_S2.B[3].BRAM [7:6];
15       <path>/p_ram_lo/BLOCKS[1].RAMB16_S2.B[2].BRAM [5:4];
16       <path>/p_ram_lo/BLOCKS[1].RAMB16_S2.B[1].BRAM [3:2];
17       <path>/p_ram_lo/BLOCKS[1].RAMB16_S2.B[0].BRAM [1:0];
18       <path>/p_ram_hi/BLOCKS[1].RAMB16_S2.B[3].BRAM [15:14];
19       <path>/p_ram_hi/BLOCKS[1].RAMB16_S2.B[2].BRAM [13:12];
20       <path>/p_ram_hi/BLOCKS[1].RAMB16_S2.B[1].BRAM [11:10];
21       <path>/p_ram_hi/BLOCKS[1].RAMB16_S2.B[0].BRAM [9:8];
22   END_BUS_BLOCK;
23 END_ADDRESS_SPACE;
24
25
26 // ram_generic: 2x4kB, BRAM_TYPE=RAMB_S4
27 ADDRESS_SPACE blockram RAMB16 [0x0200:0x21ff]
28   BUS_BLOCK
29       <path>/d_ram_lo/BLOCKS[0].RAMB16_S4.B[1].BRAM [7:4];
30       <path>/d_ram_lo/BLOCKS[0].RAMB16_S4.B[0].BRAM [3:0];
31       <path>/d_ram_hi/BLOCKS[0].RAMB16_S4.B[1].BRAM [15:12];
32       <path>/d_ram_hi/BLOCKS[0].RAMB16_S4.B[0].BRAM [11:8];
33   END_BUS_BLOCK;
34 END_ADDRESS_SPACE;
35