PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
--- halt_i : IN STD_LOGIC;
+ halt_i : IN STD_LOGIC;
int_i : IN STD_LOGIC;
-- specific fetch i/o
imem_addr_o : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
FSL_S2MEM_REG_o.S_Data <= S_Data_2r;
regd_proc:
- PROCESS ( clk_i, rst_i,
+ PROCESS ( clk_i, rst_i, halt_i,
-- complete sensitivity list for synthesizer
reset_s, MEM2CTRL_i, clken_pipe_s, IF2ID_REG_i,
flush_ID2EX_s, flush_EX2MEM_s, HAZARD_WRB_i,
END PROCEDURE;
BEGIN
- IF (RISING_EDGE (clk_i) AND (MEM2CTRL_i.clken = '1')) THEN
+ IF (RISING_EDGE (clk_i) AND (MEM2CTRL_i.clken = '1')) AND halt_i = '0' THEN
rst_r <= rst_i;
IF (reset_s = '1') THEN -- synchronous reset ...
lp_rst_IF2ID_REG; -- ... so lasts at least one clock_cycle
ID2EX_o : OUT ID2EX_Type;
--
INT_CTRL_i : IN INT_CTRL_Type;
- ID2CTRL_o : OUT ID2CTRL_Type
+ ID2CTRL_o : OUT ID2CTRL_Type;
+ --
+ noLiteOpc_s : OUT STD_LOGIC
);
END ENTITY decode;
ARCHITECTURE rtl OF decode IS
--------------------------------------------------------------------------------
- SIGNAL noLiteOpc_s : STD_LOGIC;
-
BEGIN
p_decode:
PROCESS ( prog_cntr_i, inc_pc_i, EX2IF_i )
VARIABLE next_pc_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
VARIABLE incVal_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
- VARIABLE dummy_v : STD_LOGIC;
BEGIN
incVal_v := X"0000000" & '0' & inc_pc_i & "00";
- ep_add32 ( prog_cntr_i, incVal_v, '0', next_pc_v, dummy_v);
+ ep_add32nc ( prog_cntr_i, incVal_v, '0', next_pc_v );
IF (EX2IF_i.take_branch = '0') THEN
IF2ID_o.program_counter <= next_pc_v;
ELSE
ID2EX_o : OUT ID2EX_Type;
--
INT_CTRL_i : IN INT_CTRL_Type;
- ID2CTRL_o : OUT ID2CTRL_Type
+ ID2CTRL_o : OUT ID2CTRL_Type;
+ --
+ noLiteOpc_s : OUT STD_LOGIC
);
END COMPONENT;
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
- -- halt_i : IN STD_LOGIC;
+ halt_i : IN STD_LOGIC;
int_i : IN STD_LOGIC;
-- specific fetch i/o
imem_addr_o : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
VARIABLE s : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
VARIABLE co : OUT STD_LOGIC );
+ PROCEDURE ep_add32nc ( a, b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ ci : IN STD_LOGIC;
+ VARIABLE s : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
+
-- PROCEDURE ep_add32 ( a, b : IN STD_LOGIC_VECTOR; ci : IN STD_LOGIC;
-- VARIABLE s : OUT STD_LOGIC_VECTOR;
-- VARIABLE co : OUT STD_LOGIC );
END IF;
END PROCEDURE;
+ PROCEDURE ep_add32nc ( a, b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ ci : IN STD_LOGIC;
+ VARIABLE s : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ) IS
+
+ CONSTANT NBITS_LO_c : POSITIVE := 17;
+ CONSTANT NBITS_HI_c : POSITIVE := 32 -NBITS_LO_c;
+ VARIABLE tmp_lo_v : STD_LOGIC_VECTOR (NBITS_LO_c +1 DOWNTO 0);
+ VARIABLE tmp_hi0_v : STD_LOGIC_VECTOR (NBITS_HI_c +1 DOWNTO 0);
+ VARIABLE tmp_hi1_v : STD_LOGIC_VECTOR (NBITS_HI_c +1 DOWNTO 0);
+ BEGIN
+ tmp_lo_v := STD_LOGIC_VECTOR( UNSIGNED( '0' & a(NBITS_LO_c -1 DOWNTO 0) & '1' ) +
+ UNSIGNED( '0' & b(NBITS_LO_c -1 DOWNTO 0) & ci ));
+ tmp_hi0_v := STD_LOGIC_VECTOR( UNSIGNED( '0' & a(31 DOWNTO (32 - NBITS_HI_c)) & '1') +
+ UNSIGNED( '0' & b(31 DOWNTO (32 - NBITS_HI_c)) & '0'));
+ tmp_hi1_v := STD_LOGIC_VECTOR( UNSIGNED( '0' & a(31 DOWNTO (32 - NBITS_HI_c)) & '1') +
+ UNSIGNED( '0' & b(31 DOWNTO (32 - NBITS_HI_c)) & '1'));
+ IF (tmp_lo_v(NBITS_LO_c +1) = '0') THEN
+ s := tmp_hi0_v(NBITS_HI_c DOWNTO 1) & tmp_lo_v(NBITS_LO_c DOWNTO 1);
+ ELSE
+ s := tmp_hi1_v(NBITS_HI_c DOWNTO 1) & tmp_lo_v(NBITS_LO_c DOWNTO 1);
+ END IF;
+ END PROCEDURE;
+
-- PROCEDURE ep_add32 ( a, b : IN STD_LOGIC_VECTOR; ci : IN STD_LOGIC;
-- VARIABLE s : OUT STD_LOGIC_VECTOR;
-- VARIABLE co : OUT STD_LOGIC ) IS