From b7529be7741c46ef603ef0e487642a065f3a998a Mon Sep 17 00:00:00 2001 From: Martin Meloun Date: Fri, 6 Sep 2013 12:06:23 +0200 Subject: [PATCH] Add halt and wire out bad op signal Signed-off-by: Martin Meloun --- hw/core_ctrl.vhd | 6 +++--- hw/decode.vhd | 6 +++--- hw/fetch.vhd | 3 +-- hw/mbl_Pkg.vhd | 33 +++++++++++++++++++++++++++++++-- 4 files changed, 38 insertions(+), 10 deletions(-) diff --git a/hw/core_ctrl.vhd b/hw/core_ctrl.vhd index 95289fb..596bc22 100644 --- a/hw/core_ctrl.vhd +++ b/hw/core_ctrl.vhd @@ -28,7 +28,7 @@ ENTITY core_ctrl IS PORT ( clk_i : IN STD_LOGIC; rst_i : IN STD_LOGIC; --- halt_i : IN STD_LOGIC; + halt_i : IN STD_LOGIC; int_i : IN STD_LOGIC; -- specific fetch i/o imem_addr_o : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); @@ -130,7 +130,7 @@ BEGIN FSL_S2MEM_REG_o.S_Data <= S_Data_2r; regd_proc: - PROCESS ( clk_i, rst_i, + PROCESS ( clk_i, rst_i, halt_i, -- complete sensitivity list for synthesizer reset_s, MEM2CTRL_i, clken_pipe_s, IF2ID_REG_i, flush_ID2EX_s, flush_EX2MEM_s, HAZARD_WRB_i, @@ -227,7 +227,7 @@ regd_proc: END PROCEDURE; BEGIN - IF (RISING_EDGE (clk_i) AND (MEM2CTRL_i.clken = '1')) THEN + IF (RISING_EDGE (clk_i) AND (MEM2CTRL_i.clken = '1')) AND halt_i = '0' THEN rst_r <= rst_i; IF (reset_s = '1') THEN -- synchronous reset ... lp_rst_IF2ID_REG; -- ... so lasts at least one clock_cycle diff --git a/hw/decode.vhd b/hw/decode.vhd index bee212b..b900459 100644 --- a/hw/decode.vhd +++ b/hw/decode.vhd @@ -36,7 +36,9 @@ ENTITY decode IS ID2EX_o : OUT ID2EX_Type; -- INT_CTRL_i : IN INT_CTRL_Type; - ID2CTRL_o : OUT ID2CTRL_Type + ID2CTRL_o : OUT ID2CTRL_Type; + -- + noLiteOpc_s : OUT STD_LOGIC ); END ENTITY decode; @@ -45,8 +47,6 @@ END ENTITY decode; ARCHITECTURE rtl OF decode IS -------------------------------------------------------------------------------- - SIGNAL noLiteOpc_s : STD_LOGIC; - BEGIN p_decode: diff --git a/hw/fetch.vhd b/hw/fetch.vhd index 0872293..359f816 100644 --- a/hw/fetch.vhd +++ b/hw/fetch.vhd @@ -40,10 +40,9 @@ p_fetch: PROCESS ( prog_cntr_i, inc_pc_i, EX2IF_i ) VARIABLE next_pc_v : STD_LOGIC_VECTOR (31 DOWNTO 0); VARIABLE incVal_v : STD_LOGIC_VECTOR (31 DOWNTO 0); - VARIABLE dummy_v : STD_LOGIC; BEGIN incVal_v := X"0000000" & '0' & inc_pc_i & "00"; - ep_add32 ( prog_cntr_i, incVal_v, '0', next_pc_v, dummy_v); + ep_add32nc ( prog_cntr_i, incVal_v, '0', next_pc_v ); IF (EX2IF_i.take_branch = '0') THEN IF2ID_o.program_counter <= next_pc_v; ELSE diff --git a/hw/mbl_Pkg.vhd b/hw/mbl_Pkg.vhd index 48e1162..a54495b 100644 --- a/hw/mbl_Pkg.vhd +++ b/hw/mbl_Pkg.vhd @@ -252,7 +252,9 @@ PACKAGE mbl_Pkg IS ID2EX_o : OUT ID2EX_Type; -- INT_CTRL_i : IN INT_CTRL_Type; - ID2CTRL_o : OUT ID2CTRL_Type + ID2CTRL_o : OUT ID2CTRL_Type; + -- + noLiteOpc_s : OUT STD_LOGIC ); END COMPONENT; @@ -328,7 +330,7 @@ PACKAGE mbl_Pkg IS PORT ( clk_i : IN STD_LOGIC; rst_i : IN STD_LOGIC; - -- halt_i : IN STD_LOGIC; + halt_i : IN STD_LOGIC; int_i : IN STD_LOGIC; -- specific fetch i/o imem_addr_o : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); @@ -412,6 +414,10 @@ PACKAGE mbl_Pkg IS VARIABLE s : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); VARIABLE co : OUT STD_LOGIC ); + PROCEDURE ep_add32nc ( a, b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + ci : IN STD_LOGIC; + VARIABLE s : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)); + -- PROCEDURE ep_add32 ( a, b : IN STD_LOGIC_VECTOR; ci : IN STD_LOGIC; -- VARIABLE s : OUT STD_LOGIC_VECTOR; -- VARIABLE co : OUT STD_LOGIC ); @@ -451,6 +457,29 @@ PACKAGE BODY mbl_Pkg IS END IF; END PROCEDURE; + PROCEDURE ep_add32nc ( a, b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + ci : IN STD_LOGIC; + VARIABLE s : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ) IS + + CONSTANT NBITS_LO_c : POSITIVE := 17; + CONSTANT NBITS_HI_c : POSITIVE := 32 -NBITS_LO_c; + VARIABLE tmp_lo_v : STD_LOGIC_VECTOR (NBITS_LO_c +1 DOWNTO 0); + VARIABLE tmp_hi0_v : STD_LOGIC_VECTOR (NBITS_HI_c +1 DOWNTO 0); + VARIABLE tmp_hi1_v : STD_LOGIC_VECTOR (NBITS_HI_c +1 DOWNTO 0); + BEGIN + tmp_lo_v := STD_LOGIC_VECTOR( UNSIGNED( '0' & a(NBITS_LO_c -1 DOWNTO 0) & '1' ) + + UNSIGNED( '0' & b(NBITS_LO_c -1 DOWNTO 0) & ci )); + tmp_hi0_v := STD_LOGIC_VECTOR( UNSIGNED( '0' & a(31 DOWNTO (32 - NBITS_HI_c)) & '1') + + UNSIGNED( '0' & b(31 DOWNTO (32 - NBITS_HI_c)) & '0')); + tmp_hi1_v := STD_LOGIC_VECTOR( UNSIGNED( '0' & a(31 DOWNTO (32 - NBITS_HI_c)) & '1') + + UNSIGNED( '0' & b(31 DOWNTO (32 - NBITS_HI_c)) & '1')); + IF (tmp_lo_v(NBITS_LO_c +1) = '0') THEN + s := tmp_hi0_v(NBITS_HI_c DOWNTO 1) & tmp_lo_v(NBITS_LO_c DOWNTO 1); + ELSE + s := tmp_hi1_v(NBITS_HI_c DOWNTO 1) & tmp_lo_v(NBITS_LO_c DOWNTO 1); + END IF; + END PROCEDURE; + -- PROCEDURE ep_add32 ( a, b : IN STD_LOGIC_VECTOR; ci : IN STD_LOGIC; -- VARIABLE s : OUT STD_LOGIC_VECTOR; -- VARIABLE co : OUT STD_LOGIC ) IS -- 2.39.2