reset_i : in std_logic;
-- Data bus
address_i : in std_logic_vector(4 downto 0);
- next_ce_i : in std_logic;
+ ce_i : in std_logic;
data_i : in std_logic_vector(31 downto 0);
data_o : out std_logic_vector(31 downto 0);
--
signal reset_reg_wr_s : std_logic;
--
signal reset_s : std_logic;
- signal ce_s : std_logic;
+ signal ce_r : std_logic;
begin
reset_s <= reset_reg_r or reset_i;
wire_in:
- process(next_ce_i, ce_s, reset_reg_r, bls_i, address_i, irc_data_s, data_i, irc_o_s)
+ process(ce_i, ce_r, reset_reg_r, bls_i, address_i, irc_data_s, data_i, irc_o_s)
begin
-- init values
reset_reg_wr_s <= '0';
-- Incoming bus request
- if next_ce_i = '1' then
+ if ce_i = '1' then
-- Mapping:
-- 0 & axis & irc / index - (all read from bram) (R/W)
-- 1 & axis & 0 - status register (R/W)
irc_bls_s <= bls_i;
irc_out_s <= '1';
- -- Maybe these would be better to latch in next_ce_i cycle,
+ -- Maybe these would be better to latch in ce_i cycle,
-- and then just pass them
elsif address_i(0) = '0' then
end process;
wire_out:
- process(ce_s, irc_data_s, irc_out_r, state_o_r)
+ process(ce_r, irc_data_s, irc_out_r, state_o_r)
begin
data_o <= (others => '0');
- if ce_s = '1' then
+ if ce_r = '1' then
if irc_out_r = '1' then
data_o <= irc_data_s;
process
begin
wait until clk_i'event and clk_i= '1';
- ce_s <= next_ce_i;
+ ce_r <= ce_i;
irc_out_r <= irc_out_s;
state_o_r <= state_o_s;
reset_i : in std_logic;
-- Data bus
address_i : in std_logic_vector(10 downto 0);
- next_ce_i : in std_logic;
+ ce_i : in std_logic;
data_i : in std_logic_vector(15 downto 0);
data_o : out std_logic_vector(15 downto 0);
--
signal reset_reg_wr_s : std_logic;
--
signal reset_s : std_logic;
- signal ce_s : std_logic;
+ signal ce_r : std_logic;
--
signal register_trans_in_s : std_logic;
signal register_trans_out_s : std_logic_vector(1 downto 0);
wire_in:
- process(next_ce_i, ce_s, reset_reg_r, bls_i, address_i, mem_trans_data_s,
+ process(ce_i, ce_r, reset_reg_r, bls_i, address_i, mem_trans_data_s,
mem_recv_data_s, data_i, register_trans_out_s, register_recv_out_s,
register_cycle_out_s, rx_done_ratio_r, rx_done_cnt_r)
begin
rx_done_ratio_s <= rx_done_ratio_r;
-- Incoming bus request
- if next_ce_i = '1' then
+ if ce_i = '1' then
-- Mapping:
-- 00 & xxxxxxxx - LX Master transmitter BRAM
end process;
wire_out:
- process(ce_s, mem_trans_data_s, mem_trans_out_r,
+ process(ce_r, mem_trans_data_s, mem_trans_out_r,
mem_recv_data_s, mem_recv_out_r, state_o_r)
begin
data_o <= (others => '0');
- if ce_s = '1' then
+ if ce_r = '1' then
if mem_trans_out_r = '1' then
data_o <= mem_trans_data_s;
elsif mem_recv_out_r = '1' then
process
begin
wait until clk_i'event and clk_i= '1';
- ce_s <= next_ce_i;
+ ce_r <= ce_i;
mem_trans_out_r <= mem_trans_out_s;
mem_recv_out_r <= mem_recv_out_s;
state_o_r <= state_o_s;
reset_i : in std_logic;
-- Data bus
address_i : in std_logic_vector(4 downto 0);
- next_ce_i : in std_logic;
+ ce_i : in std_logic;
data_i : in std_logic_vector(31 downto 0);
data_o : out std_logic_vector(31 downto 0);
--
constant approx_lo_used_bit : natural := 31 - approx_top_bits - approx_frac_bits + 1;
- signal ce_s : std_logic;
- signal address_s : std_logic_vector(4 downto 0);
+ signal ce_r : std_logic;
+ signal address_r : std_logic_vector(4 downto 0);
signal argument_s : std_logic_vector(31 downto 0);
signal argument_r : std_logic_vector(31 downto 0);
);
wire_in_and_next_state:
- process(next_ce_i, ce_s, bls_i, address_i, data_i, state_tab_r, argument_r)
+ process(ce_i, ce_r, bls_i, address_i, data_i, state_tab_r, argument_r)
begin
-- Incoming bus request
- if (next_ce_i = '1') and (bls_i(0) = '1') then
+ if (ce_i = '1') and (bls_i(0) = '1') then
argument_s <= data_i;
if address_i(4 downto 0) = "00001" then
state_tab_s <= ST_RECI0;
end process;
wire_out:
- process(ce_s, reci_result_r, sin_result_r, cos_result_r, address_s, argument_r)
+ process(ce_r, reci_result_r, sin_result_r, cos_result_r, address_r, argument_r)
begin
data_o <= (others => '-');
- if ce_s = '1' then
- if address_s(4 downto 0) = "00000" then
+ if ce_r = '1' then
+ if address_r(4 downto 0) = "00000" then
data_o <= x"FA00000E";
- elsif address_s(4 downto 0) = "00001" then
+ elsif address_r(4 downto 0) = "00001" then
data_o <= reci_result_r;
- elsif address_s(4 downto 0) = "00010" then
+ elsif address_r(4 downto 0) = "00010" then
data_o <= sin_result_r;
- elsif address_s(4 downto 0) = "00011" then
+ elsif address_r(4 downto 0) = "00011" then
data_o <= cos_result_r;
else
data_o <= (others => '0');
process
begin
wait until clk_i'event and clk_i= '1';
- ce_s <= next_ce_i;
- address_s <= address_i;
+ ce_r <= ce_i;
+ address_r <= address_i;
approx_frac_r <= approx_frac_s;
reset_i : in std_logic;
-- Data bus
address_i : in std_logic_vector(4 downto 0);
- next_ce_i : in std_logic;
+ ce_i : in std_logic;
data_i : in std_logic_vector(31 downto 0);
data_o : out std_logic_vector(31 downto 0);
--
reset_i : in std_logic;
-- Data bus
address_i : in std_logic_vector(4 downto 0);
- next_ce_i : in std_logic;
+ ce_i : in std_logic;
data_i : in std_logic_vector(31 downto 0);
data_o : out std_logic_vector(31 downto 0);
--
reset_i : in std_logic;
-- Data bus
address_i : in std_logic_vector(10 downto 0);
- next_ce_i : in std_logic;
+ ce_i : in std_logic;
data_i : in std_logic_vector(15 downto 0);
data_o : out std_logic_vector(15 downto 0);
--
--
clk_i => clk_50m,
address_i => tumbl_address_s(4 downto 0),
- next_ce_i => irc_proc_ce_s,
+ ce_i => irc_proc_ce_s,
data_i => tumbl_data_i_s,
data_o => irc_proc_out_s,
bls_i => tumbl_bls_s,
--
clk_i => clk_50m,
address_i => tumbl_address_s(10 downto 0),
- next_ce_i => lxmaster_ce_s,
+ ce_i => lxmaster_ce_s,
data_i => tumbl_data_i_s(15 downto 0),
data_o => lxmaster_out_s,
bls_i => tumbl_bls_s(1 downto 0),
clk_i => clk_50m,
-- Data bus
address_i => tumbl_address_s(4 downto 0),
- next_ce_i => lxfncapprox_ce_s,
+ ce_i => lxfncapprox_ce_s,
data_i => tumbl_data_i_s,
data_o => lxfncapprox_out_s,
bls_i => tumbl_bls_s
projects / fpga / lx-cpu1 / lx-rocon.git / commitdiff