From f78d0311f3719125dc63eb72b1c08acf24a893b9 Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Wed, 18 Feb 2015 23:16:38 +0100 Subject: [PATCH] Remove next_ prefix from chip selects/clock enables to reflect real phase. Signed-off-by: Pavel Pisa --- hw/bus_irc.vhd | 16 ++++++++-------- hw/bus_lxmaster.vhd | 14 +++++++------- hw/lx-fncapprox/lx_fncapprox.vhd | 26 +++++++++++++------------- hw/lx_rocon_pkg.vhd | 6 +++--- hw/lx_rocon_top.vhd | 6 +++--- 5 files changed, 34 insertions(+), 34 deletions(-) diff --git a/hw/bus_irc.vhd b/hw/bus_irc.vhd index 8221655..2a39eca 100644 --- a/hw/bus_irc.vhd +++ b/hw/bus_irc.vhd @@ -13,7 +13,7 @@ entity bus_irc is reset_i : in std_logic; -- Data bus address_i : in std_logic_vector(4 downto 0); - next_ce_i : in std_logic; + ce_i : in std_logic; data_i : in std_logic_vector(31 downto 0); data_o : out std_logic_vector(31 downto 0); -- @@ -44,7 +44,7 @@ architecture Behavioral of bus_irc is signal reset_reg_wr_s : std_logic; -- signal reset_s : std_logic; - signal ce_s : std_logic; + signal ce_r : std_logic; begin @@ -175,7 +175,7 @@ irc_proc : irc_proc_main reset_s <= reset_reg_r or reset_i; wire_in: - process(next_ce_i, ce_s, reset_reg_r, bls_i, address_i, irc_data_s, data_i, irc_o_s) + process(ce_i, ce_r, reset_reg_r, bls_i, address_i, irc_data_s, data_i, irc_o_s) begin -- init values @@ -190,7 +190,7 @@ wire_in: reset_reg_wr_s <= '0'; -- Incoming bus request - if next_ce_i = '1' then + if ce_i = '1' then -- Mapping: -- 0 & axis & irc / index - (all read from bram) (R/W) -- 1 & axis & 0 - status register (R/W) @@ -202,7 +202,7 @@ wire_in: irc_bls_s <= bls_i; irc_out_s <= '1'; - -- Maybe these would be better to latch in next_ce_i cycle, + -- Maybe these would be better to latch in ce_i cycle, -- and then just pass them elsif address_i(0) = '0' then @@ -236,12 +236,12 @@ wire_in: end process; wire_out: - process(ce_s, irc_data_s, irc_out_r, state_o_r) + process(ce_r, irc_data_s, irc_out_r, state_o_r) begin data_o <= (others => '0'); - if ce_s = '1' then + if ce_r = '1' then if irc_out_r = '1' then data_o <= irc_data_s; @@ -256,7 +256,7 @@ update: process begin wait until clk_i'event and clk_i= '1'; - ce_s <= next_ce_i; + ce_r <= ce_i; irc_out_r <= irc_out_s; state_o_r <= state_o_s; diff --git a/hw/bus_lxmaster.vhd b/hw/bus_lxmaster.vhd index 85e4262..cdb3e11 100644 --- a/hw/bus_lxmaster.vhd +++ b/hw/bus_lxmaster.vhd @@ -12,7 +12,7 @@ entity bus_lxmaster is reset_i : in std_logic; -- Data bus address_i : in std_logic_vector(10 downto 0); - next_ce_i : in std_logic; + ce_i : in std_logic; data_i : in std_logic_vector(15 downto 0); data_o : out std_logic_vector(15 downto 0); -- @@ -58,7 +58,7 @@ architecture Behavioral of bus_lxmaster is signal reset_reg_wr_s : std_logic; -- signal reset_s : std_logic; - signal ce_s : std_logic; + signal ce_r : std_logic; -- signal register_trans_in_s : std_logic; signal register_trans_out_s : std_logic_vector(1 downto 0); @@ -153,7 +153,7 @@ rx_done_divider : cnt_div wire_in: - process(next_ce_i, ce_s, reset_reg_r, bls_i, address_i, mem_trans_data_s, + process(ce_i, ce_r, reset_reg_r, bls_i, address_i, mem_trans_data_s, mem_recv_data_s, data_i, register_trans_out_s, register_recv_out_s, register_cycle_out_s, rx_done_ratio_r, rx_done_cnt_r) begin @@ -181,7 +181,7 @@ wire_in: rx_done_ratio_s <= rx_done_ratio_r; -- Incoming bus request - if next_ce_i = '1' then + if ce_i = '1' then -- Mapping: -- 00 & xxxxxxxx - LX Master transmitter BRAM @@ -272,13 +272,13 @@ wire_in: end process; wire_out: - process(ce_s, mem_trans_data_s, mem_trans_out_r, + process(ce_r, mem_trans_data_s, mem_trans_out_r, mem_recv_data_s, mem_recv_out_r, state_o_r) begin data_o <= (others => '0'); - if ce_s = '1' then + if ce_r = '1' then if mem_trans_out_r = '1' then data_o <= mem_trans_data_s; elsif mem_recv_out_r = '1' then @@ -294,7 +294,7 @@ update: process begin wait until clk_i'event and clk_i= '1'; - ce_s <= next_ce_i; + ce_r <= ce_i; mem_trans_out_r <= mem_trans_out_s; mem_recv_out_r <= mem_recv_out_s; state_o_r <= state_o_s; diff --git a/hw/lx-fncapprox/lx_fncapprox.vhd b/hw/lx-fncapprox/lx_fncapprox.vhd index 53692b9..67e27e0 100644 --- a/hw/lx-fncapprox/lx_fncapprox.vhd +++ b/hw/lx-fncapprox/lx_fncapprox.vhd @@ -12,7 +12,7 @@ entity lx_fncapprox is reset_i : in std_logic; -- Data bus address_i : in std_logic_vector(4 downto 0); - next_ce_i : in std_logic; + ce_i : in std_logic; data_i : in std_logic_vector(31 downto 0); data_o : out std_logic_vector(31 downto 0); -- @@ -42,8 +42,8 @@ architecture Behavioral of lx_fncapprox is constant approx_lo_used_bit : natural := 31 - approx_top_bits - approx_frac_bits + 1; - signal ce_s : std_logic; - signal address_s : std_logic_vector(4 downto 0); + signal ce_r : std_logic; + signal address_r : std_logic_vector(4 downto 0); signal argument_s : std_logic_vector(31 downto 0); signal argument_r : std_logic_vector(31 downto 0); @@ -167,10 +167,10 @@ sin_tab_bc : rom_table ); wire_in_and_next_state: - process(next_ce_i, ce_s, bls_i, address_i, data_i, state_tab_r, argument_r) + process(ce_i, ce_r, bls_i, address_i, data_i, state_tab_r, argument_r) begin -- Incoming bus request - if (next_ce_i = '1') and (bls_i(0) = '1') then + if (ce_i = '1') and (bls_i(0) = '1') then argument_s <= data_i; if address_i(4 downto 0) = "00001" then state_tab_s <= ST_RECI0; @@ -415,18 +415,18 @@ result_registers_write: end process; wire_out: - process(ce_s, reci_result_r, sin_result_r, cos_result_r, address_s, argument_r) + process(ce_r, reci_result_r, sin_result_r, cos_result_r, address_r, argument_r) begin data_o <= (others => '-'); - if ce_s = '1' then - if address_s(4 downto 0) = "00000" then + if ce_r = '1' then + if address_r(4 downto 0) = "00000" then data_o <= x"FA00000E"; - elsif address_s(4 downto 0) = "00001" then + elsif address_r(4 downto 0) = "00001" then data_o <= reci_result_r; - elsif address_s(4 downto 0) = "00010" then + elsif address_r(4 downto 0) = "00010" then data_o <= sin_result_r; - elsif address_s(4 downto 0) = "00011" then + elsif address_r(4 downto 0) = "00011" then data_o <= cos_result_r; else data_o <= (others => '0'); @@ -438,8 +438,8 @@ update: process begin wait until clk_i'event and clk_i= '1'; - ce_s <= next_ce_i; - address_s <= address_i; + ce_r <= ce_i; + address_r <= address_i; approx_frac_r <= approx_frac_s; diff --git a/hw/lx_rocon_pkg.vhd b/hw/lx_rocon_pkg.vhd index 59b79eb..15cc6db 100644 --- a/hw/lx_rocon_pkg.vhd +++ b/hw/lx_rocon_pkg.vhd @@ -241,7 +241,7 @@ package lx_rocon_pkg is reset_i : in std_logic; -- Data bus address_i : in std_logic_vector(4 downto 0); - next_ce_i : in std_logic; + ce_i : in std_logic; data_i : in std_logic_vector(31 downto 0); data_o : out std_logic_vector(31 downto 0); -- @@ -408,7 +408,7 @@ package lx_rocon_pkg is reset_i : in std_logic; -- Data bus address_i : in std_logic_vector(4 downto 0); - next_ce_i : in std_logic; + ce_i : in std_logic; data_i : in std_logic_vector(31 downto 0); data_o : out std_logic_vector(31 downto 0); -- @@ -496,7 +496,7 @@ package lx_rocon_pkg is reset_i : in std_logic; -- Data bus address_i : in std_logic_vector(10 downto 0); - next_ce_i : in std_logic; + ce_i : in std_logic; data_i : in std_logic_vector(15 downto 0); data_o : out std_logic_vector(15 downto 0); -- diff --git a/hw/lx_rocon_top.vhd b/hw/lx_rocon_top.vhd index 10ecdca..4b30d14 100644 --- a/hw/lx_rocon_top.vhd +++ b/hw/lx_rocon_top.vhd @@ -232,7 +232,7 @@ memory_bus_irc: bus_irc -- clk_i => clk_50m, address_i => tumbl_address_s(4 downto 0), - next_ce_i => irc_proc_ce_s, + ce_i => irc_proc_ce_s, data_i => tumbl_data_i_s, data_o => irc_proc_out_s, bls_i => tumbl_bls_s, @@ -286,7 +286,7 @@ memory_bus_lxmaster: bus_lxmaster -- clk_i => clk_50m, address_i => tumbl_address_s(10 downto 0), - next_ce_i => lxmaster_ce_s, + ce_i => lxmaster_ce_s, data_i => tumbl_data_i_s(15 downto 0), data_o => lxmaster_out_s, bls_i => tumbl_bls_s(1 downto 0), @@ -322,7 +322,7 @@ function_approx: component lx_fncapprox clk_i => clk_50m, -- Data bus address_i => tumbl_address_s(4 downto 0), - next_ce_i => lxfncapprox_ce_s, + ce_i => lxfncapprox_ce_s, data_i => tumbl_data_i_s, data_o => lxfncapprox_out_s, bls_i => tumbl_bls_s -- 2.39.2