Include initial stub of function generator to LX HW design.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>

diff --git a/hw/lx-fncapprox/lx_fncapprox.vhd b/hw/lx-fncapprox/lx_fncapprox.vhd
new file mode 100644 (file)
index 0000000..d8ed833
--- /dev/null
+++ b/hw/lx-fncapprox/lx_fncapprox.vhd
@@ -0,0 +1,110 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+use work.mbl_pkg.all;
+use work.lx_rocon_pkg.all;
+
+-- IRC bus interconnect
+entity lx_fncapprox is
+       port
+       (
+               clk_i        : in std_logic;
+               reset_i      : in std_logic;
+               -- Data bus
+               address_i    : in std_logic_vector(4 downto 0);
+               next_ce_i    : in std_logic;
+               data_i       : in std_logic_vector(31 downto 0);
+               data_o       : out std_logic_vector(31 downto 0);
+               --
+               bls_i        : in std_logic_vector(3 downto 0)
+       );
+end lx_fncapprox;
+
+architecture Behavioral of lx_fncapprox is
+
+       component rom_table
+       generic
+       (
+               data_width : integer;
+               addr_width : integer;
+               init_file  : string
+       );
+       port
+       (
+               ack_o  : out std_logic;
+               addr_i : in  std_logic_vector (addr_width-1 downto 0);
+               clk_i  : in  std_logic;
+               data_o : out std_logic_vector (data_width-1 downto 0);
+               stb_i  : in  std_logic
+       );
+       end component;
+
+       signal ce_s                 : std_logic;
+
+       signal reci_tab_idx_s       : std_logic_vector(7 downto 0);
+       signal reci_tab_idx_r       : std_logic_vector(7 downto 0);
+       signal reci_tab_a_data_s    : std_logic_vector(35 downto 0);
+       signal reci_tab_a_data_r    : std_logic_vector(35 downto 0);
+
+       signal reci_tab_a_ack_s     : std_logic;
+       signal reci_tab_a_stb_s     : std_logic;
+begin
+
+reci_tab_a : rom_table
+       generic map (
+               data_width => 36,
+               addr_width => 8,
+               init_file  => "reci_tab_a.lut"
+       )
+       port map
+       (
+               clk_i  => clk_i,
+               stb_i  => reci_tab_a_stb_s,
+               addr_i => reci_tab_idx_s,
+               data_o => reci_tab_a_data_s,
+               ack_o  => reci_tab_a_ack_s
+       );
+
+
+wire_in:
+       process(next_ce_i, ce_s, bls_i, address_i, data_i, reci_tab_idx_r)
+       begin
+               -- init values
+               reci_tab_a_stb_s     <= '0';
+               reci_tab_idx_s <= reci_tab_idx_r;
+
+               -- Incoming bus request
+               if next_ce_i = '1' then
+                       if bls_i(0) = '1' then
+                               reci_tab_a_stb_s <= '1';
+                               reci_tab_idx_s <= data_i(7 downto 0);
+                       end if;
+               end if;
+       end process;
+
+wire_out:
+       process(ce_s, reci_tab_a_data_r)
+       begin
+
+               data_o <= (others => '0');
+
+               if ce_s = '1' then
+                       data_o <= reci_tab_a_data_r(35 downto 4);
+               end if;
+       end process;
+
+update:
+       process
+       begin
+               wait until clk_i'event and clk_i= '1';
+               ce_s      <= next_ce_i;
+               if reci_tab_a_ack_s = '1' then
+                       reci_tab_a_data_r <= reci_tab_a_data_s;
+               end if;
+
+               reci_tab_idx_r <= reci_tab_idx_s;
+       end process;
+
+end Behavioral;
+

diff --git a/hw/lx-fncapprox/reci_tab_a.lut b/hw/lx-fncapprox/reci_tab_a.lut
new file mode 100644 (file)
index 0000000..0a80905
--- /dev/null
+++ b/hw/lx-fncapprox/reci_tab_a.lut
@@ -0,0 +1,256 @@
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diff --git a/hw/lx-fncapprox/reci_tab_bc.lut b/hw/lx-fncapprox/reci_tab_bc.lut
new file mode 100644 (file)
index 0000000..d74a2ef
--- /dev/null
+++ b/hw/lx-fncapprox/reci_tab_bc.lut
@@ -0,0 +1,256 @@
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+010011101111000101001010111011001001
+010011101001101000001010110110100111
+010011100100001101001010110010001000
+010011011110110100001010101101101100
+010011011001011101001010101001010001
+010011010100001001001010100100111010
+010011001110110110001010100000100100
+010011001001100110001010011100010001
+010011000100011000001010011000000001
+010010111111001011001010010011110010
+010010111010000001001010001111100110
+010010110100111001001010001011011100
+010010101111110100001010000111010101
+010010101010110000001010000011001111
+010010100101101110001001111111001100
+010010100000101111001001111011001011
+010010011011110001001001110111001100
+010010010110110110001001110011001111
+010010010001111100001001101111010101
+010010001101000100001001101011011100
+010010001000001111001001100111100110
+010010000011011011001001100011110001
+010001111110101001001001011111111111
+010001111001111010001001011100001110
+010001110101001100001001011000100000
+010001110000011111001001010100110011
+010001101011110101001001010001001001
+010001100111001100001001001101100000
+010001100010100101001001001001111001
+010001011110000000001001000110010101
+010001011001011101001001000010110010
+010001010100111011001000111111010000
+010001010000011100001000111011110001
+010001001011111111001000111000010100
+010001000111100010001000110100111000
+010001000011001000001000110001011110
+010000111110101111001000101110000101
+010000111010011000001000101010101111
+010000110110000010001000100111011010
+010000110001101111001000100100000111
+010000101101011101001000100000110110
+010000101001001100001000011101100110
+010000100100111101001000011010011000
+010000100000110000001000010111001011
+010000011100100101001000010100000000
+010000011000011011001000010000110111
+010000010100010010001000001101101111
+010000010000001011001000001010101001
+010000001100000110001000000111100101
+010000001000000011001000000100100010
+010000000100000000001000000001100000

diff --git a/hw/lx-fncapprox/rom_table.vhd b/hw/lx-fncapprox/rom_table.vhd
new file mode 100644 (file)
index 0000000..02c6f7c
--- /dev/null
+++ b/hw/lx-fncapprox/rom_table.vhd
@@ -0,0 +1,91 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library std;
+use std.textio.all;
+
+--------------------------------------------------------------------------------
+-- ROM based Up Table
+--
+-- It's based on behavioral description of full synchronous RAM, so it should be
+-- mapped into FPGA BRAM. Interface is Wishbone like. Data and address bus width
+-- is configurable.
+--
+-- Table is initialized from file specified by 'init_file' parameter. This is a
+-- text file which contains one value per line. Values are typed in binary
+-- format.  Sample file 'sin.lut' together with Matlab generation function
+-- 'gen_lut_sin.m' is enclosed.
+--------------------------------------------------------------------------------
+
+entity rom_table is
+       generic (
+               data_width : integer := 10;
+               addr_width : integer := 9;
+               init_file  : string  := "reci_tab_a.lut");
+       port (
+               ack_o  : out std_logic;
+               addr_i : in  std_logic_vector (addr_width-1 downto 0);
+               clk_i  : in  std_logic;
+               data_o : out std_logic_vector (data_width-1 downto 0);
+               stb_i  : in  std_logic
+       );
+end entity rom_table;
+
+--------------------------------------------------------------------------------
+
+architecture behavioral of rom_table is
+
+       constant table_size : integer := 2**addr_width;
+
+       type rom_table_t is array (0 to table_size-1) of bit_vector (data_width-1 downto 0);
+
+       impure function init_table_from_file (file_name : string) return rom_table_t is
+               file table_file    : text open read_mode is file_name;
+               variable file_line : line;
+               variable table     : rom_table_t;
+       begin
+               for i in rom_table_t'range loop
+                       loop
+                               if (endfile(table_file)) and (i /= 0) then
+                                       -- Repeat file data when not enough data to fill
+                                       file_close(table_file);
+                                       file_open(table_file, file_name, read_mode);
+                               end if;
+                               readline(table_file, file_line);
+                               exit when file_line'length /= 0;
+                       end loop;
+
+                       read(file_line, table(i));
+
+               end loop;
+
+               return table;
+       end function init_table_from_file;
+
+       signal ram : rom_table_t := init_table_from_file(init_file);
+
+       signal stb_delayed : std_logic;
+
+--------------------------------------------------------------------------------
+
+begin
+
+mem_context : process (clk_i, addr_i) is
+       variable address : integer;
+       begin
+               address := conv_integer(addr_i);
+
+               if rising_edge(clk_i) then
+                       stb_delayed <= stb_i;
+
+                       if stb_i = '1' then
+                               data_o <= to_stdLogicVector(ram(address));
+                       end if;
+               end if;
+       end process;
+
+       ack_o <= stb_delayed;
+
+end architecture behavioral;

diff --git a/hw/lx_rocon_pkg.vhd b/hw/lx_rocon_pkg.vhd
index 3251cd66baf1495ff52e0c3d1e582273d0860596..85bec18e83dd2ac094e809215dad9a5abd843e9b 100644 (file)
--- a/hw/lx_rocon_pkg.vhd
+++ b/hw/lx_rocon_pkg.vhd
@@ -232,6 +232,23 @@ package lx_rocon_pkg is
        );
        end component;
 
+       -- LX math functions approximation
+
+       component lx_fncapprox
+       port
+       (
+               clk_i        : in std_logic;
+               reset_i      : in std_logic;
+               -- Data bus
+               address_i    : in std_logic_vector(4 downto 0);
+               next_ce_i    : in std_logic;
+               data_i       : in std_logic_vector(31 downto 0);
+               data_o       : out std_logic_vector(31 downto 0);
+               --
+               bls_i        : in std_logic_vector(3 downto 0)
+       );
+       end component;
+
        -- Clock Cross Domain Synchronization Elastic Buffer/FIFO
        component lx_crosdom_ser_fifo
        generic

diff --git a/hw/lx_rocon_top.prj b/hw/lx_rocon_top.prj
index 3ae7f9dba8ca701fb973a8a651ea8acae0b8ffa3..503996e73bbcafc7dc1ec9a1a6810bceb199751a 100644 (file)
--- a/hw/lx_rocon_top.prj
+++ b/hw/lx_rocon_top.prj
@@ -8,6 +8,8 @@ vhdl work "tumbl/fetch.vhd"
 vhdl work "tumbl/exeq.vhd"
 vhdl work "tumbl/decode.vhd"
 vhdl work "tumbl/core_ctrl.vhd"
+vhdl work "lx-fncapprox/lx_fncapprox.vhd"
+vhdl work "lx-fncapprox/rom_table.vhd"
 vhdl work "qcounter.vhd"
 vhdl work "lx-rocon_tumbl/lx_rocon_imem.vhd"
 vhdl work "lx-rocon_tumbl/lx_rocon_gprf_abd.vhd"

diff --git a/hw/lx_rocon_top.vhd b/hw/lx_rocon_top.vhd
index 74cf8452a8692d43716643950a829913f4de3d3f..48ebe35f4fb3b8484097a0a9c2b4d5a647c9f0b8 100644 (file)
--- a/hw/lx_rocon_top.vhd
+++ b/hw/lx_rocon_top.vhd
@@ -115,6 +115,10 @@ architecture Behavioral of lx_rocon_top is
        signal lxmaster_out_s           : std_logic_vector(15 downto 0);
        signal lxmaster_ce_s            : std_logic;
        signal lxmaster_next_ce_s       : std_logic;
+       -- LX function approximation
+       signal lxfncapprox_out_s        : std_logic_vector(31 downto 0);
+       signal lxfncapprox_ce_s         : std_logic;
+       signal lxfncapprox_next_ce_s    : std_logic;
        -- Signals for external bus transmission
        signal data_i_s                 : std_logic_vector(31 downto 0);
        signal data_o_s                 : std_logic_vector(31 downto 0);
@@ -310,6 +314,19 @@ memory_bus_lxmaster: bus_lxmaster
        -- s1_sync_out     <= s2;
 
 
+function_approx: component lx_fncapprox
+       port map
+       (
+               reset_i      => reset_s,
+               clk_i        => clk_50m,
+               -- Data bus
+               address_i      => tumbl_address_s(4 downto 0),
+               next_ce_i      => lxfncapprox_next_ce_s,
+               data_i         => tumbl_data_i_s,
+               data_o         => lxfncapprox_out_s,
+               bls_i          => tumbl_bls_s
+       );
+
 -- Reset
 dff_reset: dff2
        port map
@@ -465,6 +482,7 @@ memory_bus_update:
                -- Just copy these to their desired next state
                irc_proc_ce_s <= irc_proc_next_ce_s;
                lxmaster_ce_s <= lxmaster_next_ce_s;
+               lxfncapprox_ce_s <= lxfncapprox_next_ce_s;
 
        end process;
 
@@ -535,6 +553,7 @@ tumbl_bus_o:
                -- Defaults
                irc_proc_next_ce_s        <= '0';
                lxmaster_next_ce_s        <= '0';
+               lxfncapprox_next_ce_s     <= '0';
                master_tumbl_xmem_lock_s  <= '0';
                --
                addr_v                    := (others => '0');
@@ -556,6 +575,8 @@ tumbl_bus_o:
                        -- LX MASTER: 0x1000 - 0x17FF (32-bit address)
                        if addr_v(14 downto 5) = "0001000000" then
                                irc_proc_next_ce_s     <= '1';
+                       elsif addr_v(14 downto 5) = "0001000001" then
+                               lxfncapprox_next_ce_s  <= '1';
                        elsif addr_v(14 downto 11) = "0010" then
                                lxmaster_next_ce_s     <= '1';
                        end if;
@@ -565,7 +586,8 @@ tumbl_bus_o:
 
 -- Inputs to Tumbl (enabling and address muxing)
 tumbl_bus_i:
-       process(irc_proc_ce_s, irc_proc_out_s, lxmaster_ce_s, lxmaster_out_s, tumbl_xmemb_i_s)
+       process(irc_proc_ce_s, irc_proc_out_s, lxmaster_ce_s, lxmaster_out_s,
+               lxfncapprox_ce_s, lxfncapprox_out_s, tumbl_xmemb_i_s)
        begin
 
                tumbl_xmemb_i_s.data  <= (others => 'X');
@@ -578,6 +600,8 @@ tumbl_bus_i:
                elsif lxmaster_ce_s = '1' then
                        tumbl_xmemb_i_s.data(15 downto 0)  <= lxmaster_out_s;
                        tumbl_xmemb_i_s.data(31 downto 16) <= (others => '0');
+               elsif lxfncapprox_ce_s = '1' then
+                       tumbl_xmemb_i_s.data <= lxfncapprox_out_s;
                end if;
 
                master_tumbl_xmem_out_s <= tumbl_xmemb_i_s.data;