hw/lx_rocon_top.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.all;
   4 use ieee.std_logic_unsigned.all;
   5 use ieee.numeric_std.all;
   6
   7 library unisim;
   8 use unisim.vcomponents.all;
   9
  10 use work.mbl_pkg.all;
  11 use work.lx_rocon_pkg.all;
  12
  13 -- lx_rocon_top - wires the modules with the outside world
  14
  15 -- ======================================================
  16 --  MASTER CPU EXTERNAL MEMORY BUS
  17 -- ======================================================
  18 --
  19 -- Master cpu memory bus has the following wires:
  20 --
  21 -- - address[15..0]          The address, used to mark chip enable
  22 -- - data_in[31..0]          The data coming to bus
  23 -- - data_out[31..0]         The data coming from bus, multiplexed
  24 -- - bls[3..0]               Write enable for respective bytes
  25
  26 entity lx_rocon_top is
  27         port
  28         (
  29                 -- External
  30                 --clk_cpu     : in std_logic;
  31                 clk_50m     : in std_logic;
  32                 --
  33                 cs0_xc      : in std_logic;
  34                 --
  35                 rd          : in std_logic;
  36                 bls         : in std_logic_vector(3 downto 0);
  37                 address     : in std_logic_vector(15 downto 0);
  38                 data        : inout std_logic_vector(31 downto 0);
  39                 --
  40                 irc0_a      : in std_logic;
  41                 irc0_b      : in std_logic;
  42                 irc0_index  : in std_logic;
  43                 irc0_mark   : in std_logic;
  44                 --
  45                 irc1_a      : in std_logic;
  46                 irc1_b      : in std_logic;
  47                 irc1_index  : in std_logic;
  48                 irc1_mark   : in std_logic;
  49                 --
  50                 irc2_a      : in std_logic;
  51                 irc2_b      : in std_logic;
  52                 irc2_index  : in std_logic;
  53                 irc2_mark   : in std_logic;
  54                 --
  55                 irc3_a      : in std_logic;
  56                 irc3_b      : in std_logic;
  57                 irc3_index  : in std_logic;
  58                 irc3_mark   : in std_logic;
  59                 --
  60                 irc4_a      : in std_logic;
  61                 irc4_b      : in std_logic;
  62                 irc4_index  : in std_logic;
  63                 irc4_mark   : in std_logic;
  64                 --
  65                 irc5_a      : in std_logic;
  66                 irc5_b      : in std_logic;
  67                 irc5_index  : in std_logic;
  68                 irc5_mark   : in std_logic;
  69                 --
  70                 irc6_a      : in std_logic;
  71                 irc6_b      : in std_logic;
  72                 irc6_index  : in std_logic;
  73                 irc6_mark   : in std_logic;
  74                 --
  75                 irc7_a      : in std_logic;
  76                 irc7_b      : in std_logic;
  77                 irc7_index  : in std_logic;
  78                 irc7_mark   : in std_logic;
  79                 --
  80                 init        : in std_logic;
  81                 --
  82                 s1_clk_in   : in std_logic;
  83                 s1_miso     : in std_logic;
  84                 s1_sync_in  : in std_logic;
  85                 --
  86                 s1_clk_out  : out std_logic;
  87                 s1_mosi     : out std_logic;
  88                 s1_sync_out : out std_logic;
  89                 -- signal connected to external JK FF
  90                 event_jk_j  : out std_logic
  91         );
  92 end lx_rocon_top;
  93
  94 architecture Behavioral of lx_rocon_top is
  95
  96         -- Reset signal
  97         signal reset_s                  : std_logic;
  98         signal init_s                   : std_logic;
  99         -- Peripherals on the memory buses
 100         -- Master to Tumbl DMEM / IMEM (Master)
 101         signal tumbl_out_s              : std_logic_vector(31 downto 0);
 102         signal tumbl_ce_s               : std_logic;
 103         -- Measurement (Master)
 104         signal meas_out_s               : std_logic_vector(31 downto 0);
 105         signal meas_ce_s                : std_logic;
 106         -- Master to Tumbl XMEM
 107         signal master_tumbl_xmem_out_s  : std_logic_vector(31 downto 0);
 108         signal master_tumbl_xmem_ce_s   : std_logic;
 109         signal master_tumbl_xmem_lock_s : std_logic;
 110         -- IRC (Tumbl)
 111         signal irc_proc_out_s            : std_logic_vector(31 downto 0);
 112         signal irc_proc_ce_s             : std_logic;
 113         signal irc_proc_next_ce_s        : std_logic;
 114         -- LX Master (Tumbl)
 115         signal lxmaster_out_s           : std_logic_vector(15 downto 0);
 116         signal lxmaster_ce_s            : std_logic;
 117         signal lxmaster_next_ce_s       : std_logic;
 118         -- Signals for external bus transmission
 119         signal data_i_s                 : std_logic_vector(31 downto 0);
 120         signal data_o_s                 : std_logic_vector(31 downto 0);
 121         -- Signals for internal transaction
 122         signal last_address_s           : std_logic_vector(15 downto 0);
 123         signal next_last_address_s      : std_logic_vector(15 downto 0);
 124         signal next_address_hold_s      : std_logic;
 125         signal address_hold_s           : std_logic;
 126         signal last_rd_s                : std_logic;
 127         signal next_last_rd_s           : std_logic;
 128         signal last_bls_s               : std_logic_vector(3 downto 0); -- prev bls_f_s (active 1)
 129         signal next_last_bls_s          : std_logic_vector(3 downto 0);
 130
 131         -- Reading logic for Master CPU:
 132         -- Broadcast rd only till ta (transaction acknowledge)
 133         -- is received, then latch the data till the state of
 134         -- rd or address changes
 135         --
 136         -- Data latching is synchronous - it's purpose is to
 137         -- provide stable data for CPU on the bus
 138         signal cs0_xc_f_s          : std_logic;
 139         signal rd_f_s              : std_logic; -- Filtered RD
 140         signal i_rd_s              : std_logic; -- Internal bus RD (active 1)
 141         -- signal next_i_rd_s         : std_logic;
 142         signal last_i_rd_s         : std_logic; -- Delayed RD bus, used for latching
 143         signal next_last_i_rd_s    : std_logic;
 144         signal i_rd_cycle2_s       : std_logic; -- Some internal subsystems provide
 145         signal next_i_rd_cycle2_s  : std_logic; -- data only after 2 cycles
 146         --
 147         signal address_f_s         : std_logic_vector(15 downto 0); -- Filtered address
 148         --
 149         signal data_f_s            : std_logic_vector(31 downto 0); -- Filterred input data
 150         --
 151         signal data_read_s         : std_logic_vector(31 downto 0); -- Latched read data
 152         signal next_data_read_s    : std_logic_vector(31 downto 0);
 153
 154         -- Writing logic:
 155         signal bls_f_s             : std_logic_vector(3 downto 0); -- Filtered BLS (active 1)
 156         signal i_bls_s             : std_logic_vector(3 downto 0); -- Internal BLS (active 1)
 157         signal next_i_bls_s        : std_logic_vector(3 downto 0);
 158         --
 159         signal data_write_s        : std_logic_vector(31 downto 0); -- Data broadcasted to write
 160         signal next_data_write_s   : std_logic_vector(31 downto 0);
 161
 162         -- Tumbl:
 163         signal tumbl_bls_s         : std_logic_vector(3 downto 0);
 164         signal tumbl_address_s     : std_logic_vector(14 downto 0);
 165         signal tumbl_data_i_s      : std_logic_vector(31 downto 0);
 166         --
 167         signal tumbl_xmemb_o_s     : CORE2DMEMB_Type;
 168         signal tumbl_xmemb_i_s     : DMEMB2CORE_Type;
 169         signal tumbl_xmemb_sel_s   : std_logic;
 170         -- Interrupt event sources and processing
 171         signal lxmaster_rx_done_s  : std_logic;
 172         signal lxmaster_rx_done_r  : std_logic;
 173         signal lxmaster_rx_done_last_s : std_logic;
 174         signal lxmaster_rx_done_last_r : std_logic;
 175
 176         -- signal s0   : std_logic;
 177         -- signal s1   : std_logic;
 178         -- signal s2   : std_logic;
 179
 180         -- XST attributes
 181         attribute REGISTER_DUPLICATION : string;
 182         attribute REGISTER_DUPLICATION of rd : signal is "NO";
 183         attribute REGISTER_DUPLICATION of rd_f_s : signal is "NO";
 184         attribute REGISTER_DUPLICATION of bls : signal is "NO";
 185         attribute REGISTER_DUPLICATION of bls_f_s : signal is "NO";
 186         attribute REGISTER_DUPLICATION of address : signal is "NO";
 187         attribute REGISTER_DUPLICATION of address_f_s : signal is "NO";
 188         attribute REGISTER_DUPLICATION of cs0_xc : signal is "NO";
 189
 190 begin
 191
 192 -- Tumbl coprocessor
 193 memory_bus_tumbl: bus_tumbl
 194         port map
 195         (
 196                 clk_i          => clk_50m,
 197                 reset_i        => reset_s,
 198                 ce_i           => tumbl_ce_s,
 199                 bls_i          => i_bls_s,
 200                 address_i      => address_f_s(11 downto 0),
 201                 data_i         => data_i_s,
 202                 data_o         => tumbl_out_s,
 203                 --
 204                 xmemb_o        => tumbl_xmemb_o_s,
 205                 xmemb_i        => tumbl_xmemb_i_s,
 206                 xmemb_sel_o    => tumbl_xmemb_sel_s
 207         );
 208
 209 -- Measurement
 210 memory_bus_measurement: bus_measurement
 211         port map
 212         (
 213                 clk_i     => clk_50m,
 214                 reset_i   => reset_s,
 215                 ce_i      => meas_ce_s,
 216                 address_i => address_f_s(1 downto 0),
 217                 bls_i     => i_bls_s,
 218                 data_i    => data_i_s,
 219                 data_o    => meas_out_s
 220         );
 221
 222 -- IRC interconnect
 223 memory_bus_irc: bus_irc
 224         port map
 225         (
 226                 reset_i        => reset_s,
 227                 --
 228                 clk_i          => clk_50m,
 229                 address_i      => tumbl_address_s(4 downto 0),
 230                 next_ce_i      => irc_proc_next_ce_s,
 231                 data_i         => tumbl_data_i_s,
 232                 data_o         => irc_proc_out_s,
 233                 bls_i          => tumbl_bls_s,
 234                 --
 235                 irc_i(0).a     => irc0_a,
 236                 irc_i(0).b     => irc0_b,
 237                 irc_i(0).index => irc0_index,
 238                 irc_i(0).mark  => irc0_mark,
 239                 --
 240                 irc_i(1).a     => irc1_a,
 241                 irc_i(1).b     => irc1_b,
 242                 irc_i(1).index => irc1_index,
 243                 irc_i(1).mark  => irc1_mark,
 244                 --
 245                 irc_i(2).a     => irc2_a,
 246                 irc_i(2).b     => irc2_b,
 247                 irc_i(2).index => irc2_index,
 248                 irc_i(2).mark  => irc2_mark,
 249                 --
 250                 irc_i(3).a     => irc3_a,
 251                 irc_i(3).b     => irc3_b,
 252                 irc_i(3).index => irc3_index,
 253                 irc_i(3).mark  => irc3_mark,
 254                 --
 255                 irc_i(4).a     => irc4_a,
 256                 irc_i(4).b     => irc4_b,
 257                 irc_i(4).index => irc4_index,
 258                 irc_i(4).mark  => irc4_mark,
 259                 --
 260                 irc_i(5).a     => irc5_a,
 261                 irc_i(5).b     => irc5_b,
 262                 irc_i(5).index => irc5_index,
 263                 irc_i(5).mark  => irc5_mark,
 264                 --
 265                 irc_i(6).a     => irc6_a,
 266                 irc_i(6).b     => irc6_b,
 267                 irc_i(6).index => irc6_index,
 268                 irc_i(6).mark  => irc6_mark,
 269                 --
 270                 irc_i(7).a     => irc7_a,
 271                 irc_i(7).b     => irc7_b,
 272                 irc_i(7).index => irc7_index,
 273                 irc_i(7).mark  => irc7_mark
 274         );
 275
 276 -- LX Master
 277 memory_bus_lxmaster: bus_lxmaster
 278         port map
 279         (
 280                 reset_i        => reset_s,
 281                 --
 282                 clk_i          => clk_50m,
 283                 address_i      => tumbl_address_s(10 downto 0),
 284                 next_ce_i      => lxmaster_next_ce_s,
 285                 data_i         => tumbl_data_i_s(15 downto 0),
 286                 data_o         => lxmaster_out_s,
 287                 bls_i          => tumbl_bls_s(1 downto 0),
 288                 --
 289                 rx_done_o      => lxmaster_rx_done_s,
 290                 --
 291                 clock_i        => s1_clk_in,
 292                 miso_i         => s1_miso,
 293                 sync_i         => s1_sync_in,
 294                 --
 295                 clock_o        => s1_clk_out,
 296                 mosi_o         => s1_mosi,
 297                 sync_o         => s1_sync_out
 298                 --
 299                 -- clock_i        => s0,
 300                 -- miso_i         => s1,
 301                 -- sync_i         => not s2,
 302                 --
 303                 -- clock_o        => s0,
 304                 -- mosi_o         => s1,
 305                 -- sync_o         => s2
 306         );
 307
 308         -- s1_clk_out      <= s0;
 309         -- s1_mosi         <= s1;
 310         -- s1_sync_out     <= s2;
 311
 312
 313 -- Reset
 314 dff_reset: dff2
 315         port map
 316         (
 317                 clk_i   => clk_50m,
 318                 d_i     => init_s,
 319                 q_o     => reset_s
 320         );
 321
 322         -- Reset
 323         init_s          <= not init;
 324
 325         -- Signalling
 326         data_i_s        <= data_write_s;
 327
 328         -- Tumbl
 329         tumbl_bls_s     <= i_bls_s when (master_tumbl_xmem_lock_s = '1')
 330                            else tumbl_xmemb_o_s.bls when (tumbl_xmemb_sel_s = '1')
 331                            else "0000";
 332         tumbl_address_s <= address_f_s(14 downto 0) when (master_tumbl_xmem_lock_s = '1')
 333                            else tumbl_xmemb_o_s.addr when (tumbl_xmemb_sel_s = '1')
 334                            else (others => '0');
 335         tumbl_data_i_s  <= data_i_s when (master_tumbl_xmem_lock_s = '1')
 336                            else tumbl_xmemb_o_s.data when (tumbl_xmemb_sel_s = '1')
 337                            else (others => '0');
 338         --
 339         tumbl_xmemb_i_s.int <= '0'; -- No interrupt
 340         -- Enable clken only when available for Tumbl
 341         tumbl_xmemb_i_s.clken <= not master_tumbl_xmem_lock_s;
 342
 343
 344 -- Bus update
 345 memory_bus_logic:
 346         process(cs0_xc_f_s, rd_f_s, last_rd_s, i_rd_cycle2_s, last_i_rd_s,
 347                 bls_f_s, last_bls_s, data_f_s, data_write_s,
 348                 data_o_s, data_read_s, last_address_s, address_f_s)
 349         begin
 350                 -- Defaults
 351                 next_i_rd_cycle2_s <= '0';
 352                 next_address_hold_s <= '0';
 353
 354                 -- Check if we have chip select
 355                 if cs0_xc_f_s = '1' then
 356
 357                         -- Reading
 358                         if rd_f_s = '1' then
 359                                 -- Internal read
 360                                 if last_rd_s = '0' or (last_address_s /= address_f_s) then
 361                                         i_rd_s <= '1';
 362                                         next_i_rd_cycle2_s <= '1';
 363                                         next_last_i_rd_s  <= '1';
 364                                 elsif i_rd_cycle2_s = '1' then    -- FIXME it seems that some internal
 365                                         i_rd_s <= '1';            -- peripherals demands 2 cycles to read
 366                                         next_last_i_rd_s  <= '1';
 367                                 else
 368                                         i_rd_s            <= '0';
 369                                         next_last_i_rd_s  <= '0';
 370                                 end if;
 371
 372                                 if last_i_rd_s = '1' then
 373                                         -- Latch data we just read - they are valid in this cycle
 374                                         next_data_read_s <= data_o_s;
 375                                 else
 376                                         next_data_read_s <= data_read_s;
 377                                 end if;
 378                         else
 379                         --      -- Not reading, anything goes
 380                         --      data_read_s       <= (others => 'X');
 381                                 next_data_read_s  <= data_read_s;
 382                                 i_rd_s            <= '0';
 383                                 next_last_i_rd_s  <= '0';
 384                         end if;
 385
 386                         next_last_rd_s            <= rd_f_s;
 387
 388                         -- Data for write are captured only when BLS signals are stable
 389                         if bls_f_s /= "0000" then
 390                                 next_data_write_s <= data_f_s;
 391                                 next_address_hold_s <= '1';
 392                         else
 393                                 next_data_write_s <= data_write_s;
 394                         end if;
 395
 396                         if (bls_f_s /= "0000") or (rd_f_s = '1') then
 397                                 next_last_address_s <= address_f_s;
 398                         else
 399                                 next_last_address_s <= last_address_s;
 400                         end if;
 401                 else
 402                         next_last_rd_s <= '0';
 403                         i_rd_s <= '0';
 404                         next_last_i_rd_s <= '0';
 405
 406                         next_i_bls_s <= "0000";
 407                         next_data_write_s <= data_write_s;
 408                         next_data_read_s  <= data_read_s;
 409                         next_last_address_s <= last_address_s;
 410                 end if;
 411
 412                 -- Data for write are captured at/before BLS signals are negated
 413                 -- and actual write cycle takes place exacly after BLS negation
 414                 if ((last_bls_s and not bls_f_s) /= "0000") or
 415                     ((last_bls_s /= "0000") and (cs0_xc_f_s = '0')) then
 416                         next_i_bls_s <= last_bls_s;
 417                         next_last_bls_s   <= "0000";
 418                         next_address_hold_s <= '1';
 419                 else
 420                         next_i_bls_s <= "0000";
 421                         if cs0_xc_f_s = '1' then
 422                                 next_last_bls_s <= bls_f_s;
 423                         else
 424                                 next_last_bls_s <= "0000" ;
 425                         end if;
 426                 end if;
 427
 428         end process;
 429
 430 -- Bus update
 431 memory_bus_update:
 432         process
 433         begin
 434
 435                 wait until clk_50m = '1' and clk_50m'event;
 436
 437                 address_hold_s <= next_address_hold_s;
 438
 439                 -- Synchronized external signals with main clock domain
 440                 cs0_xc_f_s     <= not cs0_xc;
 441                 bls_f_s        <= not bls;
 442                 rd_f_s         <= not rd;
 443                 data_f_s       <= data;
 444                 if address_hold_s = '0' then
 445                         address_f_s <= address;
 446                 else
 447                         address_f_s <= next_last_address_s;
 448                 end if;
 449
 450                 -- Synchronoust state andvance to next period
 451                 last_bls_s     <= next_last_bls_s;
 452                 last_rd_s      <= next_last_rd_s;
 453                 i_bls_s        <= next_i_bls_s;
 454                 -- i_rd_s         <= next_i_rd_s;
 455                 i_rd_cycle2_s  <= next_i_rd_cycle2_s;
 456                 last_i_rd_s    <= next_last_i_rd_s;
 457                 data_write_s   <= next_data_write_s;
 458                 last_address_s <= next_last_address_s;
 459                 data_read_s    <= next_data_read_s;
 460                 --
 461                 -- ======================================================
 462                 --  TUMBL BUS
 463                 -- ======================================================
 464
 465                 -- Just copy these to their desired next state
 466                 irc_proc_ce_s <= irc_proc_next_ce_s;
 467                 lxmaster_ce_s <= lxmaster_next_ce_s;
 468
 469         end process;
 470
 471 -- Do the actual wiring here
 472 memory_bus_wiring:
 473         process(cs0_xc_f_s, i_bls_s, address_f_s, tumbl_out_s, meas_out_s, master_tumbl_xmem_out_s)
 474         begin
 475
 476                 -- Inactive by default
 477                 tumbl_ce_s             <= '0';
 478                 meas_ce_s              <= '0';
 479                 master_tumbl_xmem_ce_s <= '0';
 480                 data_o_s               <= (others => '0');
 481
 482                 if cs0_xc_f_s = '1' or i_bls_s /= "0000" then
 483
 484                         -- Memory Map (16-bit address @ 32-bit each)
 485
 486                         -- Each address is seen as 32-bit entry now
 487                         -- 0x0000 - 0x0FFF: Tumbl IMEM / DMEM
 488                         -- 0x1FFC - 0x1FFF: Measurement
 489                         -- 0x8000 - 0x8FFF: Tumbl BUS
 490
 491                         if address_f_s < "0001000000000000" then                  -- Tumbl
 492                                 tumbl_ce_s             <= '1';
 493                                 data_o_s               <= tumbl_out_s;
 494                         elsif address_f_s(15 downto 2) = "00011111111111" then    -- Measurement
 495                                 meas_ce_s              <= '1';
 496                                 data_o_s               <= meas_out_s;
 497                         elsif address_f_s(15) = '1' then                          -- Tumbl External BUS
 498                                 master_tumbl_xmem_ce_s <= '1';
 499                                 data_o_s               <= master_tumbl_xmem_out_s;
 500                         end if;
 501
 502                 end if;
 503
 504         end process;
 505
 506 -- If RD and BLS is not high, we must keep DATA at high impedance
 507 -- or the FPGA collides with SDRAM (damaging each other)
 508 memory_bus_out:
 509         process(cs0_xc, rd, data_read_s)
 510         begin
 511
 512                 -- CS0 / RD / BLS are active LOW
 513                 if cs0_xc = '0' and rd = '0' then
 514                         -- Don't risk flipping (between data_o_s and latched data_read_s, it's better to wait)
 515                         -- Maybe check this later.
 516                         -- if last_i_rd_s = '1' then
 517                         --   data <= data_o_s;
 518                         -- else
 519                         data <= data_read_s;
 520                         -- end if;
 521                 else
 522                         -- IMPORTANT!!!
 523                         data <= (others => 'Z');
 524                 end if;
 525
 526         end process;
 527
 528 -- Outputs from Tumbl (enabling and address muxing) and Master CPU
 529 tumbl_bus_o:
 530         process(tumbl_xmemb_sel_s, tumbl_xmemb_o_s, master_tumbl_xmem_ce_s, address_f_s, i_rd_s, i_bls_s)
 531                 variable addr_v : std_logic_vector(14 downto 0); -- This space is visible by both (32-bit)
 532                 variable sel_v  : std_logic;
 533         begin
 534
 535                 -- Defaults
 536                 irc_proc_next_ce_s        <= '0';
 537                 lxmaster_next_ce_s        <= '0';
 538                 master_tumbl_xmem_lock_s  <= '0';
 539                 --
 540                 addr_v                    := (others => '0');
 541                 sel_v                     := '0';
 542
 543                 -- Check who is accessing
 544                 if master_tumbl_xmem_ce_s = '1' and (i_rd_s = '1' or i_bls_s /= "0000") then
 545                         -- Master blocks Tumbl
 546                         master_tumbl_xmem_lock_s <= '1';
 547                         addr_v                   := address_f_s(14 downto 0);
 548                         sel_v                    := '1';
 549                 else
 550                         addr_v                   := tumbl_xmemb_o_s.addr;
 551                         sel_v                    := '1';
 552                 end if;
 553
 554                 if sel_v = '1' then
 555                         -- IRC:       0x0800 - 0x081F (32-bit address)
 556                         -- LX MASTER: 0x1000 - 0x17FF (32-bit address)
 557                         if addr_v(14 downto 5) = "0001000000" then
 558                                 irc_proc_next_ce_s     <= '1';
 559                         elsif addr_v(14 downto 11) = "0010" then
 560                                 lxmaster_next_ce_s     <= '1';
 561                         end if;
 562                 end if;
 563
 564         end process;
 565
 566 -- Inputs to Tumbl (enabling and address muxing)
 567 tumbl_bus_i:
 568         process(irc_proc_ce_s, irc_proc_out_s, lxmaster_ce_s, lxmaster_out_s, tumbl_xmemb_i_s)
 569         begin
 570
 571                 tumbl_xmemb_i_s.data  <= (others => 'X');
 572
 573                 -- NOTE: This is input to Tumbl EXEQ - with MUL instruction for input > 18-bit,
 574                 -- (i.e. more DSPs in a sequence), this already has tough timing constraints
 575                 -- and SmartXplorer has to be used with XiSE or use Synplify.
 576                 if irc_proc_ce_s = '1' then
 577                         tumbl_xmemb_i_s.data <= irc_proc_out_s;
 578                 elsif lxmaster_ce_s = '1' then
 579                         tumbl_xmemb_i_s.data(15 downto 0)  <= lxmaster_out_s;
 580                         tumbl_xmemb_i_s.data(31 downto 16) <= (others => '0');
 581                 end if;
 582
 583                 master_tumbl_xmem_out_s <= tumbl_xmemb_i_s.data;
 584
 585         end process;
 586
 587 events_logic:
 588         process(lxmaster_rx_done_r, lxmaster_rx_done_last_r)
 589         begin
 590                 event_jk_j <= lxmaster_rx_done_r or lxmaster_rx_done_last_r;
 591                 lxmaster_rx_done_last_s <= lxmaster_rx_done_r;
 592         end process;
 593
 594 events_update:
 595         process
 596         begin
 597                 wait until clk_50m = '1' and clk_50m'event;
 598
 599                 lxmaster_rx_done_r <= lxmaster_rx_done_s;
 600                 lxmaster_rx_done_last_r <= lxmaster_rx_done_last_s;
 601         end process;
 602
 603 end Behavioral;
 604