long pxmc_rocon_irc_offset[PXML_MAIN_CNT];
unsigned pxmc_rocon_mark_filt[PXML_MAIN_CNT];
+unsigned pxmc_rocon_lxpwr_chips = 0;
static inline
pxmc_rocon_state_t *pxmc_state2rocon_state(pxmc_state_t *mcs)
}
int
-pxmc_rocon_pwm_master_init(void)
+pxmc_rocon_pwm_master_setup(unsigned lxpwr_chips)
{
int i;
int grp_in = 0;
int grp_out = 0;
unsigned word_slot;
unsigned receiver_done_div = 1;
+ unsigned lxpwr_chips_max = 2;
#ifdef LXPWR_WITH_SIROLADC
unsigned lxpwr_header = 1;
unsigned lxpwr_words = 1 + 8 * 2 + 2;
- unsigned lxpwr_chips = 2;
unsigned lxpwr_chip_pwm_cnt = 8;
#else /*LXPWR_WITH_SIROLADC*/
unsigned lxpwr_header = 0;
unsigned lxpwr_words = 8;
- unsigned lxpwr_chips = 2;
unsigned lxpwr_chip_pwm_cnt = 8;
#endif /*LXPWR_WITH_SIROLADC*/
*fpga_lx_master_receiver_done_div = receiver_done_div << 8;
pxmc_rocon_rx_done_sqn_inc = receiver_done_div;
- for (i = 0; i < LX_MASTER_DATA_OFFS + lxpwr_words * lxpwr_chips; i++)
+ if (lxpwr_chips > lxpwr_chips_max)
+ return -1;
+
+ for (i = 0; i < LX_MASTER_DATA_OFFS + lxpwr_words * lxpwr_chips_max; i++)
fpga_lx_master_receiver_base[i] = 0;
+ if (lxpwr_chips >= 2) {
+ word_slot = LX_MASTER_DATA_OFFS + lxpwr_words;
+ fpga_lx_master_receiver_base[grp_in++] = (word_slot << 8) | lxpwr_words;
+ }
+
word_slot = LX_MASTER_DATA_OFFS;
fpga_lx_master_receiver_base[grp_in++] = (word_slot << 8) | lxpwr_words;
+
fpga_lx_master_receiver_base[grp_in++] = 0x0000;
- for (i = 0; i < LX_MASTER_DATA_OFFS + lxpwr_words * lxpwr_chips; i++)
+ for (i = 0; i < LX_MASTER_DATA_OFFS + lxpwr_words * lxpwr_chips_max; i++)
fpga_lx_master_transmitter_base[i] = 0;
word_slot = LX_MASTER_DATA_OFFS + lxpwr_header + lxpwr_chip_pwm_cnt;
return 0;
}
+int
+pxmc_rocon_wait_rx_done(void)
+{
+ uint32_t sqn_last;
+ uint32_t sqn_act;
+ uint32_t timeout = 10000;
+
+ sqn_last = *fpga_lx_master_receiver_done_div;
+ sqn_last = sqn_last & 0x1f;
+
+ do {
+ sqn_act = *fpga_lx_master_receiver_done_div;
+ sqn_act = sqn_act & 0x1f;
+ if (sqn_act != sqn_last)
+ return 0;
+ } while(timeout--);
+
+ return -1;
+}
+
+int
+pxmc_rocon_pwm_master_init(void)
+{
+ int res;
+ volatile uint32_t *lxpwr_header_ptr;
+ unsigned lxpwr_words = 1 + 8 * 2 + 2;
+
+ pxmc_rocon_lxpwr_chips = 0;
+
+ res = pxmc_rocon_pwm_master_setup(2);
+ if (res < 0)
+ return 0;
+
+ if (pxmc_rocon_wait_rx_done() < 0)
+ return -1;
+ if (pxmc_rocon_wait_rx_done() < 0)
+ return -1;
+
+ lxpwr_header_ptr = fpga_lx_master_receiver_base;
+ lxpwr_header_ptr += LX_MASTER_DATA_OFFS;
+
+ if (lxpwr_header_ptr[0] == 0xb100 + lxpwr_words - 1) {
+ if (lxpwr_header_ptr[lxpwr_words] == 0xb100 + lxpwr_words - 1) {
+ pxmc_rocon_lxpwr_chips = 2;
+ return 2;
+ }
+ return -1;
+ }
+
+ if (lxpwr_header_ptr[lxpwr_words] != 0xb100 + lxpwr_words - 1) {
+ return -1;
+ }
+
+ res = pxmc_rocon_pwm_master_setup(1);
+ if (res < 0)
+ return 0;
+
+ if (pxmc_rocon_wait_rx_done() < 0)
+ return -1;
+ if (pxmc_rocon_wait_rx_done() < 0)
+ return -1;
+
+ if (lxpwr_header_ptr[0] != 0xb100 + lxpwr_words - 1)
+ return -1;
+
+ pxmc_rocon_lxpwr_chips = 1;
+
+ return 1;
+}
+
int pxmc_ptofs_from_index(pxmc_state_t *mcs, unsigned long irc,
unsigned long index_irc, int diff2err)
{
int res;
int i;
+ pxmc_main_list.pxml_cnt = 0;
+ pxmc_dbg_hist = NULL;
+ #ifdef PXMC_ROCON_TIMED_BY_RX_DONE
+ disable_irq(ROCON_RX_IRQn);
+ #endif /*PXMC_ROCON_TIMED_BY_RX_DONE*/
+ __memory_barrier();
+
pxmc_state_t *mcs = &mcs0.base;
lpc_qei_state_t *qst = &lpc_qei_state;
/*pxmc_ctm4pwm3f_wr(mcs, 0, 0, 0);*/
//pxmc_rocon_pwm3ph_wr(mcs, 0, 0, 0);
- pxmc_rocon_pwm_master_init();
+ res = pxmc_rocon_pwm_master_init();
+ if (res < 0)
+ return -1;
+
#ifdef PXMC_ROCON_TIMED_BY_RX_DONE
pxmc_rocon_rx_done_isr_setup(pxmc_rocon_rx_done_isr);
#endif /*PXMC_ROCON_TIMED_BY_RX_DONE*/
- pxmc_main_list.pxml_cnt = 0;
- pxmc_dbg_hist = NULL;
__memory_barrier();
pxmc_main_list.pxml_cnt = PXML_MAIN_CNT;