+int
+pxmc_rocon_wait_rx_done(void)
+{
+ uint32_t sqn_last;
+ uint32_t sqn_act;
+ uint32_t timeout = 10000;
+
+ sqn_last = *fpga_lx_master_receiver_done_div;
+ sqn_last = sqn_last & 0x1f;
+
+ do {
+ sqn_act = *fpga_lx_master_receiver_done_div;
+ sqn_act = sqn_act & 0x1f;
+ if (sqn_act != sqn_last)
+ return 0;
+ } while(timeout--);
+
+ return -1;
+}
+
+int
+pxmc_rocon_pwm_master_init(void)
+{
+ int res;
+ volatile uint32_t *lxpwr_header_ptr;
+ unsigned lxpwr_words = 1 + 8 * 2 + 2;
+
+ pxmc_rocon_lxpwr_chips = 0;
+
+ res = pxmc_rocon_pwm_master_setup(2);
+ if (res < 0)
+ return 0;
+
+ if (pxmc_rocon_wait_rx_done() < 0)
+ return -1;
+ if (pxmc_rocon_wait_rx_done() < 0)
+ return -1;
+
+ lxpwr_header_ptr = fpga_lx_master_receiver_base;
+ lxpwr_header_ptr += LX_MASTER_DATA_OFFS;
+
+ if (lxpwr_header_ptr[0] == 0xb100 + lxpwr_words - 1) {
+ if (lxpwr_header_ptr[lxpwr_words] == 0xb100 + lxpwr_words - 1) {
+ pxmc_rocon_lxpwr_chips = 2;
+ return 2;
+ }
+ return -1;
+ }
+
+ if (lxpwr_header_ptr[lxpwr_words] != 0xb100 + lxpwr_words - 1) {
+ return -1;
+ }
+
+ res = pxmc_rocon_pwm_master_setup(1);
+ if (res < 0)
+ return 0;
+
+ if (pxmc_rocon_wait_rx_done() < 0)
+ return -1;
+ if (pxmc_rocon_wait_rx_done() < 0)
+ return -1;
+
+ if (lxpwr_header_ptr[0] != 0xb100 + lxpwr_words - 1)
+ return -1;
+
+ pxmc_rocon_lxpwr_chips = 1;
+
+ return 1;
+}
+