Tumbl - disable GPRF forward if finish_wrb_mem_s is clock cycle cause.

[fpga/lx-cpu1/lx-rocon.git] / hw / lx_rocon_pkg.vhd

diff --git a/hw/lx_rocon_pkg.vhd b/hw/lx_rocon_pkg.vhd
index f81465295c1d673a5baacb91b30f30b594433d2a..59b79ebd04e0a8418f3c854025e3c2bee66e87ce 100644 (file)
--- a/hw/lx_rocon_pkg.vhd
+++ b/hw/lx_rocon_pkg.vhd
@@ -157,8 +157,26 @@ package lx_rocon_pkg is
   );
        end component;
 
-       -- LX Master
+       -- Counter - divider
+       component cnt_div
+       generic (
+               cnt_width_g : natural := 8
+       );
+       port
+       (
+               clk_i     : in std_logic;
+               en_i      : in std_logic;
+               reset_i   : in std_logic;
+               ratio_i   : in std_logic_vector(cnt_width_g-1 downto 0);
+               q_out_o   : out std_logic
+       );
+       end component;
+
+       -- LX Master transmitter
        component lxmaster_transmitter
+       generic (
+               cycle_cnt_width_g : natural := 12
+       );
        port
        (
                clk_i             : in std_logic;
@@ -171,6 +189,10 @@ package lx_rocon_pkg is
                register_i        : in std_logic;
                register_o        : out std_logic_vector(1 downto 0);
                register_we_i     : in std_logic;
+               -- Cycle period
+               cycle_reg_i       : in std_logic_vector(cycle_cnt_width_g-1 downto 0);
+               cycle_reg_o       : out std_logic_vector(cycle_cnt_width_g-1 downto 0);
+               cycle_reg_we_i    : in std_logic;
                -- Watchdog
                wdog_i            : in std_logic;
                wdog_we_i         : in std_logic;
@@ -184,6 +206,72 @@ package lx_rocon_pkg is
        );
        end component;
 
+       -- LX Master receiver
+       component lxmaster_receiver
+       port
+       (
+               clk_i             : in std_logic;
+               reset_i           : in std_logic;
+               -- Transmision
+               clock_i           : in std_logic;
+               miso_i            : in std_logic;
+               sync_i            : in std_logic;
+               -- Receive done pulse
+               rx_done_o         : out std_logic;
+               -- Register
+               register_i        : in std_logic;
+               register_o        : out std_logic_vector(1 downto 0);
+               register_we_i     : in std_logic;
+               -- BRAM access
+               mem_clk_i         : in std_logic;
+               mem_en_i          : in std_logic;
+               mem_we_i          : in std_logic_vector(1 downto 0);
+               mem_addr_i        : in std_logic_vector(8 downto 0);
+               mem_data_i        : in std_logic_vector(15 downto 0);
+               mem_data_o        : out std_logic_vector(15 downto 0)
+       );
+       end component;
+
+       -- LX math functions approximation
+
+       component lx_fncapprox
+       port
+       (
+               clk_i        : in std_logic;
+               reset_i      : in std_logic;
+               -- Data bus
+               address_i    : in std_logic_vector(4 downto 0);
+               next_ce_i    : in std_logic;
+               data_i       : in std_logic_vector(31 downto 0);
+               data_o       : out std_logic_vector(31 downto 0);
+               --
+               bls_i        : in std_logic_vector(3 downto 0)
+       );
+       end component;
+
+       -- Clock Cross Domain Synchronization Elastic Buffer/FIFO
+       component lx_crosdom_ser_fifo
+       generic
+       (
+               fifo_len_g   : positive := 8;
+               sync_adj_g   : integer := 0
+       );
+       port
+       (
+               -- Asynchronous clock domain interface
+               acd_clock_i  : in std_logic;
+               acd_miso_i   : in std_logic;
+               acd_sync_i   : in std_logic;
+               -- Clock
+               clk_i        : in std_logic;
+               reset_i      : in std_logic;
+               -- Output synchronous with clk_i
+               miso_o       : out std_logic;
+               sync_o       : out std_logic;
+               data_ready_o : out std_logic
+       );
+       end component;
+
        --------------------------------------------------------------------------------
        -- TUMBL
        --------------------------------------------------------------------------------
@@ -276,6 +364,7 @@ package lx_rocon_pkg is
                clk_i        :  in std_logic;
                rst_i        :  in std_logic;
                clken_i      :  in std_logic;
+               gprf_finish_wrb_mem_i :  in std_logic;
                --
                ID2GPRF_i    :  in ID2GPRF_Type;
                MEM_WRB_i    :  in WRB_Type;
@@ -412,6 +501,8 @@ package lx_rocon_pkg is
                data_o       : out std_logic_vector(15 downto 0);
                --
                bls_i        : in std_logic_vector(1 downto 0);
+               --
+               rx_done_o    : out std_logic;
                -- Signals for LX Master
                clock_i      : in std_logic;
                miso_i       : in std_logic;