Implement reset properly with correct polarity inside the modules

[fpga/lx-cpu1/lx-rocon.git] / hw / qcounter.vhd

diff --git a/hw/qcounter.vhd b/hw/qcounter.vhd
index 8df047f7f34c6bc1e739a42b4f7a52ad436680f6..8bbb9139832f78c28457545cd0f63b8cbe001837 100644 (file)
--- a/hw/qcounter.vhd
+++ b/hw/qcounter.vhd
@@ -57,7 +57,7 @@ begin
        qcount(1) <= b;
        qcount(31 downto 2) <= count;
 
-  comb_event: process (a_prev, b_prev, a, b)
+  comb_event: process (reset, a_prev, b_prev, a, b)
   begin
     a_rise <= '0';
     a_fall <= '0';
@@ -65,21 +65,26 @@ begin
     b_fall <= '0';
     ab_event <= '0';
     ab_error <= '0';
-    if ((a xor a_prev) and (b xor b_prev)) = '1' then
-      -- forbidden double transition
-      ab_error <= '1';
-    else
-      a_rise <= (a xor a_prev) and a;
-      a_fall <= (a xor a_prev) and not a;
-      b_rise <= (b xor b_prev) and b;
-      b_fall <= (b xor b_prev) and not b;
-      ab_event <= (a xor a_prev) or (b xor b_prev);
-    end if;
+
+               if reset = '0' then
+                       if ((a xor a_prev) and (b xor b_prev)) = '1' then
+                               -- forbidden double transition
+                               ab_error <= '1';
+                       else
+                               a_rise <= (a xor a_prev) and a;
+                               a_fall <= (a xor a_prev) and not a;
+                               b_rise <= (b xor b_prev) and b;
+                               b_fall <= (b xor b_prev) and not b;
+                               ab_event <= (a xor a_prev) or (b xor b_prev);
+                       end if;
+               end if;
   end process;
 
-  comb_count: process (a_prev, b_prev, a, b, count, count_prev)
+  comb_count: process (reset, a_prev, b_prev, a, b, count, count_prev)
   begin
-    if (a_prev = '0') and (b_prev = '1') and (a = '0') and (b = '0') then
+               if reset = '1' then
+                       count <= count_prev;
+               elsif (a_prev = '0') and (b_prev = '1') and (a = '0') and (b = '0') then
       count <= count_prev + 1;
     elsif (a_prev = '0') and (b_prev = '0') and (a = '0') and (b = '1') then
       count <= count_prev - 1;
@@ -88,15 +93,16 @@ begin
     end if;
   end process;
 
-  seq: process (clk)
+  seq: process (clk, reset, a, b)
   begin
-    if clk = '1' and clk'event then
+    if reset = '1' then
+                       count_prev <= (others => '0');
+               end if;
+
+               if clk = '1' and clk'event then
                        if reset = '0' then
-                               count_prev <= (others => '0');
-                       else
                                count_prev <= count;
                        end if;
-
                        a_prev <= a;
                        b_prev <= b;
                end if;