Implement reset properly with correct polarity inside the modules

[fpga/lx-cpu1/lx-rocon.git] / hw / lx_rocon_top.vhd

diff --git a/hw/lx_rocon_top.vhd b/hw/lx_rocon_top.vhd
index 3b7b33bd751ca2c4cad377813e2153ecb6f79fd7..538b33dab968e4feebf835be7741f5ef38bd00cf 100644 (file)
--- a/hw/lx_rocon_top.vhd
+++ b/hw/lx_rocon_top.vhd
@@ -390,8 +390,7 @@ begin
        end process;
 
        -- If RD and BLS is not high, we must keep DATA at high impedance
-       -- or the FPGA collides with SDRAM (burning each other)
-
+       -- or the FPGA collides with SDRAM (damaging each other)
        memory_bus_out: process(cs0_xc, rd, data, data_read)
        begin
 
@@ -411,7 +410,7 @@ begin
        initialization: process(init)
        begin
 
-               reset <= init;
+               reset <= not init;
 
        end process;