#include <LPC17xx.h>
#include <lpcTIM.h>
#include <spi_drv.h>
+#include <pxmc.h>
+#include <inttypes.h>
#include <ul_log.h>
#include <ul_logreg.h>
#include "appl_defs.h"
#include "appl_fpga.h"
+#include "pxmcc_types.h"
int cmd_do_test_memusage(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
{
}
#endif /*SDRAM_BASE*/
-#define LXPWR_RX_TIM LPC_TIM2
-#define LXPWR_RX_IRQn TIMER2_IRQn
+int cmd_do_testlxpwrrx(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+ char *ps = param[1];
+ long mode = 0;
+ uint32_t *ptr;
+
+ if (ps != NULL) {
+ si_skspace(&ps);
+ if (*ps) {
+ if (si_ulong(&ps, &mode, 0) < 0)
+ return -CMDERR_BADPAR;
+ }
+ }
+ pxmc_rocon_rx_data_hist_buff = NULL;
+ pxmc_rocon_rx_data_hist_mode = mode;
+
+ #ifndef PXMC_ROCON_TIMED_BY_RX_DONE
+ pxmc_rocon_rx_done_isr_setup(pxmc_rocon_rx_done_isr);
+ #endif /*PXMC_ROCON_TIMED_BY_RX_DONE*/
+ pxmc_rocon_rx_data_hist_buff_end = (void *)(FPGA_CONFIGURATION_FILE_ADDRESS +
+ 0x80000);
+ ptr = (void *)FPGA_CONFIGURATION_FILE_ADDRESS;
+ if (mode != 0) {
+ *(ptr++) = '10XL';
+ *(ptr++) = mode;
+ }
+ pxmc_rocon_rx_data_hist_buff = (void *)ptr;
+ return 0;
+}
-volatile void *lxpwr_rx_data_hist_buff;
-volatile void *lxpwr_rx_data_hist_buff_end;
+int cmd_do_testlxpwrstat(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+ printf("lxpwrrx period %ld latency %ld max %ld\n",
+ (long)pxmc_rocon_rx_cycle_time, (long)pxmc_rocon_rx_irq_latency,
+ (long)pxmc_rocon_rx_irq_latency_max);
+ return 0;
+}
-uint32_t lxpwr_rx_last_irq;
-uint32_t lxpwr_rx_cycle_time;
-uint32_t lxpwr_rx_irq_latency;
-uint32_t lxpwr_rx_irq_latency_max;
+#include <math.h>
-IRQ_HANDLER_FNC(lxpwr_rx_done_isr)
+int cmd_do_testfncapprox(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
{
- uint32_t ir;
-
- ir = LXPWR_RX_TIM->IR & LPC_TIM_IR_ALL_m;
- LXPWR_RX_TIM->IR = ir;
- if (ir & LPC_TIM_IR_CR1INT_m) {
- uint32_t cr0, cr1;
- cr0 = LXPWR_RX_TIM->CR0;
- cr1 = LXPWR_RX_TIM->CR1;
-
- lxpwr_rx_cycle_time = cr1 - lxpwr_rx_last_irq;
- lxpwr_rx_last_irq = cr1;
-
- hal_gpio_set_value(T2MAT0_PIN, 1);
- hal_gpio_set_value(T2MAT1_PIN, 0);
- hal_gpio_set_value(T2MAT0_PIN, 0);
-
- if (lxpwr_rx_data_hist_buff >= lxpwr_rx_data_hist_buff_end)
- lxpwr_rx_data_hist_buff = NULL;
-
- if (lxpwr_rx_data_hist_buff != NULL) {
- int i;
- volatile uint32_t *pwm_reg = fpga_lx_master_transmitter_base + 8;
- volatile uint32_t *rec_reg = fpga_lx_master_receiver_base + 8;
- uint16_t *pbuf = (uint16_t *)lxpwr_rx_data_hist_buff;
- for (i = 0; i < 8; i++) {
- *(pbuf++) = *(rec_reg++);
- }
- for (i = 0; i < 8; i++) {
- *(pbuf++) = *(pwm_reg++);
- }
- lxpwr_rx_data_hist_buff = pbuf;
+ char *ps = param[1];
+ unsigned long fnc;
+ unsigned long val;
+ unsigned long res;
+ long diff;
+ long diff_max = 0;
+ unsigned int xb;
+ uint32_t x;
+ uint32_t xl;
+ double xf;
+ int64_t yl;
+ long count = 1;
+ long step = 1 << (30-7-18+1 +4);
+
+ si_skspace(&ps);
+ if (si_ulong(&ps, &fnc, 0) < 0)
+ return -CMDERR_BADPAR;
+
+ si_skspace(&ps);
+ if (!strcmp(ps, "all")) {
+ val = 0;
+ count = 0x80000000UL / step;
+ if (fnc == 1) {
+ val = 1;
}
+ } else {
+ if (si_ulong(&ps, &val, 0) < 0)
+ return -CMDERR_BADPAR;
+ }
+
+ for (; count--; val += step) {
+
+ if (fnc == 1) {
+ x = val;
+ xb = __builtin_clz(x);
+ xl = x << xb;
+ } else {
+ xl = val;
+ }
+
+ fpga_fncapprox_base[fnc] = xl;
+
+ /* dummy read to provide time to function aproximator to proceed computation */
+ res = fpga_fncapprox_base[fnc];
+ res = fpga_fncapprox_base[fnc];
+
+ switch (fnc) {
+ case 0:
+ yl = xl;
+ case 1:
+ yl = (1LL << 62) / xl;
+ break;
+ case 2:
+ xf = (double)xl * M_PI / 2.0 / (1UL << 30);
+ yl = round(sin(xf) * (1UL << 16));
+ break;
+ case 3:
+ xf = (double)xl * M_PI / 2.0 / (1UL << 30);
+ yl = round(cos(xf) * (1UL << 16));
+ break;
+ default:
+ yl = 0;
+ }
+
+ diff = yl - res;
+
+ if ((diff > 0) && (diff > diff_max))
+ diff_max = diff;
+ else if ((diff < 0) && (-diff > diff_max))
+ diff_max = -diff;
- lxpwr_rx_irq_latency = LXPWR_RX_TIM->TC - cr1;
- if (lxpwr_rx_irq_latency > lxpwr_rx_irq_latency_max)
- lxpwr_rx_irq_latency_max = lxpwr_rx_irq_latency;
}
- return IRQ_HANDLED;
+ val -= step;
+
+ printf("fnc=%ld val=0x%08lx res=0x%08lx ref=0x%08lx diff=%ld max %ld\n",
+ fnc, val, res, (unsigned long)yl, diff, diff_max);
+
+ return 0;
}
-int lxpwr_rx_done_isr_init(void)
+int cmd_do_testtumblefw(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
{
+ char *ps = param[1];
+ long pwm_d;
+ long pwm_q;
+ uint32_t ptofs;
+ uint32_t irc;
+ uint32_t ptirc;
+ uint32_t ptreci;
+ uint32_t pwmtx_info;
+ uint64_t ull;
+ pxmc_state_t *mcs = pxmc_main_list.pxml_arr[0];
+ volatile pxmcc_data_t *mcc_data = (pxmcc_data_t *)fpga_tumbl_dmem;
+ volatile pxmcc_axis_data_t *mcc_axis = mcc_data->axis + 0;
+
+ mcc_axis->ccflg = 0;
+
+ si_skspace(&ps);
+ if (si_long(&ps, &pwm_d, 0) < 0)
+ return -CMDERR_BADPAR;
- disable_irq(LXPWR_RX_IRQn);
+ si_skspace(&ps);
+ if (si_ulong(&ps, &pwm_q, 0) < 0)
+ return -CMDERR_BADPAR;
- hal_pin_conf_set(T2MAT0_PIN, PORT_CONF_GPIO_OUT_LO);
- hal_pin_conf_set(T2MAT1_PIN, PORT_CONF_GPIO_OUT_LO);
- hal_pin_conf(T2CAP0_PIN);
- hal_pin_conf(T2CAP1_PIN);
+ irc = fpga_irc[0]->count;
+ ptofs = (int16_t)(mcs->pxms_ptofs - irc) + irc;
- hal_gpio_direction_output(T2MAT0_PIN, 1);
- hal_gpio_direction_output(T2MAT1_PIN, 0);
- hal_gpio_set_value(T2MAT0_PIN, 0);
+ ptirc = mcs->pxms_ptirc;
+ ull = (1ULL << 32) * mcs->pxms_ptper;
+ ptreci = (ull + ptirc / 2) / ptirc;
- /* Enable CLKOUT pin function, source CCLK, divide by 1 */
- LPC_SC->CLKOUTCFG = 0x0100;
+ pwmtx_info = (9 << 0) | (10 << 8) | (11 << 16);
- request_irq(LXPWR_RX_IRQn, lxpwr_rx_done_isr, 0, NULL,NULL);
+ mcc_axis->inp_info = mcs->pxms_inp_info;
+ mcc_axis->out_info = mcs->pxms_out_info;
+ mcc_axis->pwmtx_info = pwmtx_info;
- LXPWR_RX_TIM->TCR = 0;
- LXPWR_RX_TIM->CTCR = 0;
- LXPWR_RX_TIM->PR = 0; /* Divide by 1 */
+ mcc_axis->ptirc = ptirc;
+ mcc_axis->ptreci = ptreci;
+ mcc_axis->ptofs = ptofs;
- LXPWR_RX_TIM->CCR = LPC_TIM_CCR_CAP0RE_m | LPC_TIM_CCR_CAP1FE_m |
- LPC_TIM_CCR_CAP1I_m;
+ mcc_axis->ccflg = 0;
+ mcc_axis->pwm_dq = (pwm_d << 16) | (pwm_q & 0xffff);
- LXPWR_RX_TIM->EMR = __val2mfld(LPC_TIM_EMR_EMC0_m, LPC_TIM_EMR_NOP) |
- __val2mfld(LPC_TIM_EMR_EMC1_m, LPC_TIM_EMR_NOP);
+ pxmc_clear_flags(mcs,PXMS_ENO_m|PXMS_ENG_m|PXMS_ENR_m|PXMS_BSY_m);
- LXPWR_RX_TIM->MCR = 0; /* No IRQ on MRx */
- LXPWR_RX_TIM->TCR = LPC_TIM_TCR_CEN_m; /* Enable timer counting */
- enable_irq(LXPWR_RX_IRQn); /* Enable interrupt */
+ mcc_axis->ccflg = 1;
- return 0;
+ if (0) {
+ mcc_data->axis[1].pwmtx_info = (12 << 0) | (13 << 8) | (14 << 16);
+ mcc_data->axis[1].ccflg = 1;
+ mcc_data->axis[2].pwmtx_info = (12 << 0) | (13 << 8) | (14 << 16);
+ mcc_data->axis[2].ccflg = 1;
+ mcc_data->axis[3].pwmtx_info = (12 << 0) | (13 << 8) | (14 << 16);
+ mcc_data->axis[3].ccflg = 1;
+ }
-}
+ printf("spd %ld act_idle %"PRIu32" min_idle %"PRIu32" avail %lu pwm_cycle %"PRIu32"\n",
+ mcs->pxms_as, mcc_data->common.act_idle, mcc_data->common.min_idle,
+ (mcc_data->common.pwm_cycle + 6) / 6, mcc_data->common.pwm_cycle);
+ mcc_data->common.min_idle = 0x7fff;
-int cmd_do_testlxpwrrx(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
-{
- lxpwr_rx_data_hist_buff = NULL;
- lxpwr_rx_done_isr_init();
- lxpwr_rx_data_hist_buff_end = (void *)(FPGA_CONFIGURATION_FILE_ADDRESS +
- 0x80000);
- lxpwr_rx_data_hist_buff = (void *)FPGA_CONFIGURATION_FILE_ADDRESS;
return 0;
}
-int cmd_do_testlxpwrstat(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+#define CK_IRC_WORDS 16
+#define CK_TX_WORDS 16
+#define CK_RX_WORDS 16
+
+#define CK_IRC_START ((uint32_t*)fpga_irc[0])
+#define CK_TX_START (fpga_lx_master_transmitter_base+9)
+#define CK_RX_START (fpga_lx_master_receiver_base+44)
+
+typedef struct ck_state_t {
+ uint32_t ck_irc_base[CK_IRC_WORDS];
+ uint32_t ck_irc_read[CK_IRC_WORDS];
+ uint32_t ck_tx_base[CK_TX_WORDS];
+ uint32_t ck_tx_read[CK_TX_WORDS];
+ uint32_t ck_rx_base[CK_RX_WORDS];
+ uint32_t ck_rx_read[CK_RX_WORDS];
+
+ uint32_t ck_irc_err;
+ uint32_t ck_tx_err;
+ uint32_t ck_rx_err;
+} ck_state_t;
+
+int cmd_do_testtumblebus(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
{
- printf("lxpwrrx period %ld latency %ld max %ld\n",
- (long)lxpwr_rx_cycle_time, (long)lxpwr_rx_irq_latency,
- (long)lxpwr_rx_irq_latency_max);
+ int i;
+ int cycles = 10000;
+ static ck_state_t *ckst = NULL;
+ if (ckst == NULL)
+ ckst = malloc(sizeof(*ckst));
+ if (ckst == NULL)
+ return 1;
+
+ ckst->ck_irc_err = 0;
+ ckst->ck_tx_err = 0;
+ ckst->ck_rx_err = 0;
+
+ for (i = 0; i < CK_IRC_WORDS; i++)
+ ckst->ck_irc_base[i] = CK_IRC_START[i];
+
+ for (i = 0; i < CK_TX_WORDS; i++)
+ ckst->ck_tx_base[i] = CK_TX_START[i];
+
+ for (i = 0; i < CK_RX_WORDS; i++)
+ ckst->ck_rx_base[i] = CK_RX_START[i];
+
+ while (cycles--) {
+ if (!ckst->ck_irc_err) {
+ for (i = 0; i < CK_IRC_WORDS; i++)
+ ckst->ck_irc_read[i] = CK_IRC_START[i];
+ for (i = 0; i < CK_IRC_WORDS; i++)
+ if (ckst->ck_irc_read[i] != ckst->ck_irc_base[i]) {
+ ckst->ck_irc_err++;
+ printf("irc+%x %08"PRIx32" != %08"PRIx32"\n",
+ i, ckst->ck_irc_read[i], ckst->ck_irc_base[i]);
+ }
+ }
+
+ if (!ckst->ck_tx_err) {
+ for (i = 0; i < CK_TX_WORDS; i++)
+ ckst->ck_tx_read[i] = CK_TX_START[i];
+ for (i = 0; i < CK_TX_WORDS; i++)
+ if (ckst->ck_tx_read[i] != ckst->ck_tx_base[i]) {
+ ckst->ck_tx_err++;
+ printf("tx+%x %08"PRIx32" != %08"PRIx32"\n",
+ i, ckst->ck_tx_read[i], ckst->ck_tx_base[i]);
+ }
+ }
+
+ if (!ckst->ck_rx_err) {
+ for (i = 0; i < CK_RX_WORDS; i++)
+ ckst->ck_rx_read[i] = CK_RX_START[i];
+ for (i = 0; i < CK_RX_WORDS; i++)
+ if (ckst->ck_rx_read[i] != ckst->ck_rx_base[i]) {
+ ckst->ck_rx_err++;
+ printf("rx+%x %08"PRIx32" != %08"PRIx32"\n",
+ i, ckst->ck_rx_read[i], ckst->ck_rx_base[i]);
+ }
+ }
+ }
+
return 0;
}
cmd_do_testlxpwrstat, {(void *)0}
};
+cmd_des_t const cmd_des_testfncapprox = {0, 0,
+ "testfncapprox", "test of function approximator",
+ cmd_do_testfncapprox, {(void *)0}
+ };
+
+cmd_des_t const cmd_des_testtumblefw = {0, 0,
+ "testtumblefw", "test Tumble coprocesor firmware",
+ cmd_do_testtumblefw, {(void *)0}
+ };
+
+cmd_des_t const cmd_des_testtumblebus = {0, 0,
+ "testtumblebus", "test Tumble coprocesor bus",
+ cmd_do_testtumblebus, {(void *)0}
+ };
+
+
cmd_des_t const *const cmd_appl_tests[] =
{
&cmd_des_test_memusage,
#endif /*SDRAM_BASE*/
&cmd_des_testlxpwrrx,
&cmd_des_testlxpwrstat,
+ &cmd_des_testfncapprox,
+ &cmd_des_testtumblefw,
+ &cmd_des_testtumblebus,
NULL
};
projects / fpga / lx-cpu1 / lx-rocon.git / blobdiff