Remove next_ prefix from chip selects/clock enables to reflect real phase.

[fpga/lx-cpu1/lx-rocon.git] / hw / bus_irc.vhd

diff --git a/hw/bus_irc.vhd b/hw/bus_irc.vhd
index 8221655ffdf36e04e58f485de85fa641aaac5bb7..2a39eca5c55fc40ef199997b6bb101d4bcb1a76a 100644 (file)
--- a/hw/bus_irc.vhd
+++ b/hw/bus_irc.vhd
@@ -13,7 +13,7 @@ entity bus_irc is
                reset_i      : in std_logic;
                -- Data bus
                address_i    : in std_logic_vector(4 downto 0);
-               next_ce_i    : in std_logic;
+               ce_i         : in std_logic;
                data_i       : in std_logic_vector(31 downto 0);
                data_o       : out std_logic_vector(31 downto 0);
                --
@@ -44,7 +44,7 @@ architecture Behavioral of bus_irc is
        signal reset_reg_wr_s       : std_logic;
        --
        signal reset_s              : std_logic;
-       signal ce_s                 : std_logic;
+       signal ce_r                 : std_logic;
 
 begin
 
@@ -175,7 +175,7 @@ irc_proc : irc_proc_main
        reset_s <= reset_reg_r or reset_i;
 
 wire_in:
-       process(next_ce_i, ce_s, reset_reg_r, bls_i, address_i, irc_data_s, data_i, irc_o_s)
+       process(ce_i, ce_r, reset_reg_r, bls_i, address_i, irc_data_s, data_i, irc_o_s)
        begin
 
                -- init values
@@ -190,7 +190,7 @@ wire_in:
                reset_reg_wr_s       <= '0';
 
                -- Incoming bus request
-               if next_ce_i = '1' then
+               if ce_i = '1' then
                        -- Mapping:
                        -- 0 & axis & irc / index - (all read from bram) (R/W)
                        -- 1 & axis & 0           - status register (R/W)
@@ -202,7 +202,7 @@ wire_in:
                                irc_bls_s     <= bls_i;
                                irc_out_s     <= '1';
 
-                       -- Maybe these would be better to latch in next_ce_i cycle,
+                       -- Maybe these would be better to latch in ce_i cycle,
                        -- and then just pass them
                        elsif address_i(0) = '0' then
 
@@ -236,12 +236,12 @@ wire_in:
        end process;
 
 wire_out:
-       process(ce_s, irc_data_s, irc_out_r, state_o_r)
+       process(ce_r, irc_data_s, irc_out_r, state_o_r)
        begin
 
                data_o <= (others => '0');
 
-               if ce_s = '1' then
+               if ce_r = '1' then
 
                        if irc_out_r = '1' then
                                data_o <= irc_data_s;
@@ -256,7 +256,7 @@ update:
        process
        begin
                wait until clk_i'event and clk_i= '1';
-               ce_s      <= next_ce_i;
+               ce_r      <= ce_i;
                irc_out_r <= irc_out_s;
                state_o_r <= state_o_s;