hw/xilinx_dualport_bram_no_change.vhd

   1 -- Xilinx dualport BRAM template, write-first mode, no delay
   2 library ieee;
   3 use ieee.std_logic_1164.all;
   4 use ieee.numeric_std.all;
   5 use work.lx_rocon_pkg.all;
   6
   7 entity xilinx_dualport_bram_no_change is
   8         generic
   9         (
  10                 -- Not all combinations are plausible for BRAMs
  11                 -- byte width: 8, 9, 32, 36
  12                 -- we_width: 1, 2, 3, 4
  13                 byte_width : positive := 8;
  14                 address_width : positive := 8;
  15                 we_width : positive := 4
  16         );
  17         port
  18         (
  19                 clka : in std_logic;
  20                 rsta : in std_logic;
  21                 ena : in std_logic;
  22                 wea : in std_logic_vector((we_width-1) downto 0);
  23                 addra : in std_logic_vector((address_width-1) downto 0);
  24                 dina : in std_logic_vector(((byte_width*we_width)-1) downto 0);
  25                 douta : out std_logic_vector(((byte_width*we_width)-1) downto 0);
  26                 clkb : in std_logic;
  27                 rstb : in std_logic;
  28                 enb : in std_logic;
  29                 web : in std_logic_vector((we_width-1) downto 0);
  30                 addrb : in std_logic_vector((address_width-1) downto 0);
  31                 dinb : in std_logic_vector(((byte_width*we_width)-1) downto 0);
  32                 doutb : out std_logic_vector(((byte_width*we_width)-1) downto 0)
  33         );
  34 end xilinx_dualport_bram_no_change;
  35
  36 architecture Behavioral of xilinx_dualport_bram_no_change is
  37         type ram is array (0 to ((2**address_width) - 1)) of std_logic_vector(((byte_width*we_width)-1) downto 0);
  38         shared variable ram_block : ram := (others => (others => '0'));
  39
  40 begin
  41
  42 -- CLKA process
  43 ram_process_a:
  44         process
  45         begin
  46
  47                 wait until clka'event and clka = '1';
  48
  49                 if ena = '1' then
  50
  51                         for i in 0 to (we_width-1) loop
  52                                 if wea(i) = '1' then
  53                                         ram_block(to_integer(unsigned(addra)))(((i+1)*byte_width-1) downto (i*byte_width))
  54                                                 := dina(((i+1)*byte_width-1) downto (i*byte_width));
  55                                 end if;
  56                         end loop;
  57
  58                         if to_integer(unsigned(wea)) = 0 then
  59                                 if rsta = '1' then
  60                                         douta <= (others => '0');
  61                                 else
  62                                         douta <= ram_block(to_integer(unsigned(addra)));
  63                                 end if;
  64                         end if;
  65
  66                 end if;
  67
  68         end process;
  69
  70 -- CLKB process
  71 ram_process_b:
  72         process
  73         begin
  74
  75                 wait until clkb'event and clkb = '1';
  76
  77                 if enb = '1' then
  78
  79                         for i in 0 to (we_width-1) loop
  80                                 if web(i) = '1' then
  81                                         ram_block(to_integer(unsigned(addrb)))(((i+1)*byte_width-1) downto (i*byte_width))
  82                                                 := dinb(((i+1)*byte_width-1) downto (i*byte_width));
  83                                 end if;
  84                         end loop;
  85
  86                         if to_integer(unsigned(web)) = 0 then
  87                                 if rstb = '1' then
  88                                         doutb <= (others => '0');
  89                                 else
  90                                         doutb <= ram_block(to_integer(unsigned(addrb)));
  91                                 end if;
  92                         end if;
  93
  94                 end if;
  95
  96         end process;
  97
  98 end Behavioral;