sw/app/rocon/appl_fpga.h

   1 #ifndef _APPL_FPGA_H
   2 #define _APPL_FPGA_H
   3
   4 #include "appl_defs.h"
   5
   6 /* Register defines */
   7
   8 /* Tumbl */
   9
  10 #define FPGA_TUMBL_IMEM_BASE      0x80000000
  11 #define FPGA_TUMBL_DMEM_BASE      0x80001000
  12 #define FPGA_TUMBL_CONTROL_REG    0x80003000
  13 #define FPGA_TUMBL_TRACE_KICK_REG 0x80003004
  14 #define FPGA_TUMBL_PC             0x80003008
  15
  16 #define FPGA_TUMBL_CONTROL_REG_RESET_BIT 0x01
  17 #define FPGA_TUMBL_CONTROL_REG_INT_BIT   0x02
  18 #define FPGA_TUMBL_CONTROL_REG_HALT_BIT  0x04
  19 #define FPGA_TUMBL_CONTROL_REG_TRACE_BIT 0x08
  20
  21 extern volatile uint32_t *fpga_tumbl_control;
  22 extern volatile uint32_t *fpga_tumbl_trace_kick;
  23 extern volatile uint32_t *fpga_tumbl_pc;
  24 extern volatile uint32_t *fpga_tumbl_imem;
  25 extern volatile uint32_t *fpga_tumbl_dmem;
  26
  27 /* IRC */
  28
  29 #define FPGA_IRC0_BASE    0x80022000
  30 #define FPGA_IRC1_BASE    0x80022008
  31 #define FPGA_IRC2_BASE    0x80022010
  32 #define FPGA_IRC3_BASE    0x80022018
  33 #define FPGA_IRC4_BASE    0x80022020
  34 #define FPGA_IRC5_BASE    0x80022028
  35 #define FPGA_IRC6_BASE    0x80022030
  36 #define FPGA_IRC7_BASE    0x80022038
  37
  38 #define FPGA_IRC_RESET    0x80022044
  39
  40 struct irc_register
  41 {
  42   int32_t count;
  43   int32_t count_index;
  44 };
  45
  46 extern volatile struct irc_register *fpga_irc1;
  47 extern volatile struct irc_register *fpga_irc2;
  48 extern volatile struct irc_register *fpga_irc3;
  49 extern volatile struct irc_register *fpga_irc4;
  50 extern volatile struct irc_register *fpga_irc5;
  51 extern volatile struct irc_register *fpga_irc6;
  52 extern volatile struct irc_register *fpga_irc7;
  53 extern volatile struct irc_register *fpga_irc8;
  54
  55 extern volatile struct irc_register *fpga_irc[8];
  56
  57 /* Masks */
  58 #define FPGA_IRC_STATE_MARK_MASK              0x00000001
  59 #define FPGA_IRC_STATE_AB_ERROR_MASK          0x00000002
  60 #define FPGA_IRC_STATE_INDEX_EVENT_MASK       0x00000004
  61 #define FPGA_IRC_STATE_INDEX_MASK             0x00000008
  62
  63 #define FPGA_IRC_STATE_RESET_AB_ERROR_MASK    0x00000002
  64 #define FPGA_IRC_STATE_RESET_INDEX_EVENT_MASK 0x00000004
  65
  66 extern volatile uint8_t *fpga_irc1_state;
  67 extern volatile uint8_t *fpga_irc2_state;
  68 extern volatile uint8_t *fpga_irc3_state;
  69 extern volatile uint8_t *fpga_irc4_state;
  70 extern volatile uint8_t *fpga_irc6_state;
  71 extern volatile uint8_t *fpga_irc5_state;
  72 extern volatile uint8_t *fpga_irc7_state;
  73 extern volatile uint8_t *fpga_irc8_state;
  74
  75 extern volatile uint8_t *fpga_irc_state[8];
  76
  77 extern volatile uint8_t *fpga_irc_reset;
  78
  79 /* LX Master */
  80
  81 #if 0 /* FPGA design version 2 */
  82 #define FPGA_LX_MASTER_TRANSMITTER_BASE   0x80023000
  83 #define FPGA_LX_MASTER_RECEIVER_BASE      0x80023804
  84 #define FPGA_LX_MASTER_RESET              0x80023800
  85 #else /* FPGA design version 3 */
  86 #define FPGA_LX_MASTER_TRANSMITTER_BASE   0x80024000
  87 #define FPGA_LX_MASTER_RECEIVER_BASE      0x80024800
  88 #define FPGA_LX_MASTER_RESET              0x80025000
  89 #endif
  90 #define FPGA_LX_MASTER_TRANSMITTER_REG    0x80025004
  91 #define FPGA_LX_MASTER_TRANSMITTER_WDOG   0x80025008
  92 #define FPGA_LX_MASTER_TRANSMITTER_CYCLE  0x8002500C
  93 #define FPGA_LX_MASTER_RECEIVER_REG       0x80025010
  94 #define FPGA_LX_MASTER_RECEIVER_DONE_DIV  0x80025014
  95
  96 extern volatile uint32_t *fpga_lx_master_transmitter_base;
  97 extern volatile uint32_t *fpga_lx_master_transmitter_reg;
  98 extern volatile uint32_t *fpga_lx_master_transmitter_cycle;
  99 extern volatile uint32_t *fpga_lx_master_transmitter_wdog;
 100 extern volatile uint32_t *fpga_lx_master_receiver_base;
 101 extern volatile uint32_t *fpga_lx_master_receiver_reg;
 102 extern volatile uint32_t *fpga_lx_master_reset;
 103 extern volatile uint32_t *fpga_lx_master_conf;
 104
 105 extern volatile uint32_t *fpga_lx_master_transmitter_control_reg;
 106 extern volatile uint32_t *fpga_lx_master_receiver_control_reg;
 107 extern volatile uint32_t *fpga_lx_master_receiver_done_div;
 108
 109 #define FPGA_LX_MASTER_CONTROL_ADDRESS_MASK     0x0000FF00
 110 #define FPGA_LX_MASTER_CONTROL_DATA_LENGTH_MASK 0x000000FF
 111
 112 /* Function approximation block */
 113
 114 #define FPGA_FNCAPPROX_BASE               0x80023000
 115
 116 extern volatile uint32_t *fpga_fncapprox_base;
 117
 118 /* Configuration defines */
 119
 120 #define FPGA_CONFIGURATION_FILE_ADDRESS 0xA1C00000
 121
 122 #define FPGA_CONF_SUCESS              0
 123 #define FPGA_CONF_ERR_RECONF_LOCKED   1
 124 #define FPGA_CONF_ERR_RESET_FAIL      2
 125 #define FPGA_CONF_ERR_WRITE_ERR       3
 126 #define FPGA_CONF_ERR_CRC_ERR         4
 127
 128 int fpga_tumbl_set_reset(int reset);
 129 int fpga_tumbl_set_halt(int halt);
 130 int fpga_tumbl_set_trace(int trace);
 131 int fpga_tumbl_kick_trace();
 132
 133 void fpga_tumbl_write(unsigned int offset, unsigned char *ptr, int len);
 134
 135 int (*fpga_reconfiguaration_initiated)(void);
 136 int (*fpga_reconfiguaration_finished)(void);
 137
 138 void fpga_init();
 139 int fpga_configure();
 140 int fpga_measure_bus_read();
 141 int fpga_measure_bus_write();
 142 void fpga_set_reconfiguration_lock(int lock);
 143 int fpga_get_reconfiguration_lock();
 144
 145 #endif /*_APPL_FPGA_H*/